Z16C0210VSC00TR Zilog, Z16C0210VSC00TR Datasheet - Page 6

• Manufacturer Part Number: Z16C0210VSC00TR
• Description: IC Z16C00 MPU 44PLCC
• Manufacturer: Zilog

Specifications of Z16C0210VSC00TR

• Processor Type: Z16C01/C02
• Features: Low Power CMOS
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4
5
6
8
9
18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
AC CHARACTERISTICS
No.
1
2
3
7
10
11
12
13
14
15
16
1.7
19
6
TdC(Az)
TdA(DR)
TsDR(C)
TdDS(A)
TdC(DW)’ Clock + Write Data Valid
ThDR(DS) Read Data to /DS Rise Hold Time
TdDW(DS) Write Data Valid to /DS Rise Delay
TdA( MR)
TdC(MR)
TwMRh
TdMR(A)
TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay
TdMR(DR) /MREQ [Read Data Required Valid
TdC(MR)
TdC(ASf)
TdA(AS)
TdC(ASr)
TdAS( DR)
TdDS(AS) /DS + /AS Fall Delay
TwAS
TdAz(DSR) Address Float to /DS (Read) Fall Delay
TdAS(DSR) /AS t /DS (Read) Fall Delay
TdDSR(DR) /DS (Read) Fall to Read Data Required Valid
TdC(DSr)
TdDS(DW) /DS + Write Data Not Valid
TdA( DSR)
TdC(DSR) Clock Rise /DS (Read) Fall Delay
TwDSR
TdC(DSWj
TwDSW
TdDSI(DR) /DS (l/O) [ Read Data Required Valid
TdC(DSf)
TwDS
TdAS(DSA) /AS t /DS (Acknowledge) Fall Delay
TdC(DSA)
TdDSA(DR) /DS (Acknowledge) [ Read Data Required Delay
TdC(S)
Symbol
TcC
TwCh
TwCl
TfC
TrC
TdC(SNv)
TdC(SNn)
TdC(Bz)
TdC(A)
TdAS(A)
, Clock t Bus Float
Address Valid to Read Data Required Valid
/DStAddress Active
Address Valid to /MREQ Fall Delay
Clock Fall to /MREQ Fall Delay
/MREQ Width (High)
/MREQ [ Address Not Active
Address Valid to /AS Rise Delay
Clock [ /AS Rise Delay
/AS + Read Data Required Valid
/AS Width (Low)
/AS t Address Not Active Delay
Address Valid to /DS (Read) Fall Delay
/DS (Read) Width (Low)
Clock Fall to /DS (Write) Fall Delay
/DS (Write) Width (Low)
/DS (l/O) Width (Low)
Parameter
Clock Cycle Time
Clock Width (High)
Clock Width (Low) -
Clock Fall Time
Clock Rise Time
Clock+ Segment Number Valid (50pf load)
Clock tsegment Number Not Valid
Clock tAddress Valid
Clock + Address Float
Read Data to Clock Fall Setup Time
Clock Fall /MREQ Rise Delay
Clock + /AS Fall Delay
Clock Fall to /OS Rise Delay
Clock [ /DS (l/O) Fall Delay
Clock + /DS (Acknowledge) Fall Delay
Clock Rise to Status Valid Delay
216CO1/2
40
40
0
20
45*
0
20
80
20
20
20*
35*
30
0
25*
65*
110*
75*
160
410*
Min
100
110*
15*
10 MHz
50
50
50
50
60
50
50
35
25
35*
80
30
45
45
45
45
50
Max
**
**
**
10
10
180
140*
140
120*
165*
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