IDT79RC32V364-133DA IDT, Integrated Device Technology Inc, IDT79RC32V364-133DA Datasheet
IDT79RC32V364-133DA
Specifications of IDT79RC32V364-133DA
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IDT79RC32V364-133DA Summary of contents
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Features Features Features Features High-performance embedded RISController microprocessor, based on IDT RISCore32300 core – Based on MIPS 32 RISC architecture with enhancements – Scalar 5-stage pipeline minimizes branch and load delays – 66 Million multiply accumulate (MAC) Mul-Add/second @ 133MHz ...
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Device Ov Device Overview erview Device Device Ov Ov erview erview Targeted to a variety of performance-hungry, cost-sensitive embedded applications, the RC32364 is a new low-powered, low-cost member of the Integrated Device Technology, Inc. (IDT) RISController Series of Embedded ...
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Two atomic operations—multiply-add (MAD) and multiply-subtract (MSUB)—are used to perform the multiply-accumulate and multiply- subtract operations. The MAD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the ...
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This allows the system architect to allocate address space according to the most efficient use of bus bandwidth. For example, stack data may be accessed always as write-back, while packet data may be best accessed as write through, for ...
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RC32364 also provides Ack*, Retry*, and BusErr* signals. This device also provides I/D* signals, to indicate whether instructions or data is being transferred. The Last* signal is provided to indicate that the last data transfer is in progress. The ...
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Clock Serial PIO Pin Description Table Pin Description Table Pin Description Table Pin Description Table The following is a list of the system interface pins available on the RC32364. Pin names ending with an asterisk (*) are active when ...
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Pin Type Width(1:0) O Bus Width Indicates the Physical Memory/IO data bus size as follows: BE*(3:0) O ByteEnables(3:0)/Addr(1:0) Indicates which byte lanes are expected to participate in the transfer. CIP* O Cycle-in-progress Denotes that a cycle is in progress. ...
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Pin Type Retry* I Retry Indicates that the current bus cycle must be terminated. Retry* is ignored after acceptance of the first data during a read cycle. Dur- ing a write, Retry* is recognized in all data cycles. Initialization ...
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Pin Type PCST(2:0) I/O PCST(2:0)/ModeBit(2:0) PC Trace Status Information 111 (STL) Pipe line Stall 110 (JMP) Branch/Jump forms with PC output 101 (BRT) Branch/Jump forms with no PC output 100 (EXP) Exception generated with an exception vector code output ...
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Logic Diagram Logic Diagram Logic Diagram Logic Diagram Figure 2 illustrates the direction and functional groupings for the processor signals of the RC32364. MasterClk TCK TDI/DINT* TDO/TPC TMS TRST* DCLK PCST(2:0) PCST(4:3) DebugBoot ...
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RC32364 144-pin TQFP Package Pin-Out RC32364 144-pin TQFP Package Pin-Out RC32364 144-pin TQFP Package Pin-Out RC32364 144-pin TQFP Package Pin-Out Note that the asterisk (*) identifies an active-low pin. For maximum flexibility and future design compatibility, N.C. pins should ...
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Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of ...
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ystem Interface Parameters—RC32364 ystem Interface Parameters—RC32364 ystem Interface Parameters—RC32364 ystem Interface Parameters—RC32364 Parameter Data Output Data Output Hold Data Output for ALE Data Setup Data Setup Special: Ack, Retry, BusErr t Data Hold JTAG Clock ...
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Output Loading For AC Testing Output Loading For AC Testing Output Loading For AC Testing Output Loading For AC Testing Power Consumption — — — — RC32364 Power Consumption Power Consumption Power Consumption Parameter System Condition standby ...
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Power Curves Power Curves Power Curves Power Curves The following two graphs contain power curves that show power consumption at various bus frequencies. Note: Only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported. ...
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Timing Characteristics — RC32364 Timing Characteristics — RC32364 Timing Characteristics — RC32364 Timing Characteristics — RC32364 MasterClock Input Output ALE Ack* Retry* BusErr* VCC MasterClock (MClk) ColdReset* Reset* ModeBit[9:0] t MCKP t t MCKLOW MCKHIGH t MCRISE t DS ...
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Standard JTAG Timing Standard JTAG Timing Standard JTAG Timing Standard JTAG Timing Figure 8 represents the timing diagram for the EJTAG interface signals. The standard JTAG connector is a 10-pin connector providing 5 signal and 5 ground pins. For ...
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Table 4 shows the pin numbering for the Standard EJTAG (EJT) connector. All the even numbered pins are connected to GROUND. The two right- hand most columns show the target signal direction and the recommended termination at the target. ...
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RC32364 Package Drawing — 144-pin TQFP RC32364 Package Drawing — 144-pin TQFP RC32364 Package Drawing — 144-pin TQFP RC32364 Package Drawing — 144-pin TQFP (Note: The RC32364 is available in a 144-pin thin quad flat pack (TQFP) package.) 19 ...
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RC32364 Package Drawing RC32364 Package Drawing RC32364 Package Drawing RC32364 Package Drawing — — — — Page Two Page Two Page Two Page Two *Notice: The information in this document is subject to change without notice ...
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... Product Operating Device Type Voltage Valid Combinations Valid Combinations Valid Combinations Valid Combinations IDT79RC32V364 - 100,133 DA IDT79RC32V364 - 100,133 DAI CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a trademark of Integrated Device Technology, Inc. XXXX 999 A Package Speed ...