IDT79RC32V332-150DHG IDT, Integrated Device Technology Inc, IDT79RC32V332-150DHG Datasheet
IDT79RC32V332-150DHG
Specifications of IDT79RC32V332-150DHG
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IDT79RC32V332-150DHG Summary of contents
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Device Overview The RC32332 device is a member of the IDT™ Interprise™ family of integrated communications processors. This product incorporates a high-performance, low-cost 32-bit CPU core with functionality common to a large number of embedded applications. The RC32332 integrates these ...
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IDT 79RC32332 ◆ Serial Peripheral Interface (SPI) master mode interface ◆ UART Interface – 16550 compatible UART – Baud rate support up to 1.5 Mb/s ◆ Memory & Peripheral Controller – 6 banks 8MB per bank – Supports ...
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IDT 79RC32332 ◆ 2KB of 2-way set associative data cache, capable of write-back and write-through operation. ◆ Cache locking per line to speed real-time systems and critical system functions ◆ On-chip TLB to enable multi-tasking in modern operating systems EJTAG ...
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IDT 79RC32332 Secondly, the RC32332 implements additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. This product allows the logic analyzer to differentiate transac- tions initiated by DMA from those initiated by the ...
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IDT 79RC32332 Pin Description Table The following table lists the pins provided on the RC32332. Note that those pin names followed by “_n” are active-low signals. All external pull-ups and pull-downs require 10 kΩ resistor. Reset Name Type State Status ...
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IDT 79RC32332 Reset Name Type State Status mem_wait_n Input mem_245_oe_n Output H mem_245_dt_r_n Output Z output_clk Output cpu_mas terclk PCI Interface pci_ad[31:0] I/O Z pci_cbe_n[3:0] I/O Z pci_par I/O Z pci_frame_n I/O Z pci_trdy_n I/O Z pci_irdy_n I/O Z pci_stop_n ...
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IDT 79RC32332 Reset Name Type State Status pci_req_n[2] Input Z pci_req_n[0] I pci_gnt_n[2] Output Z pci_gnt_n[1] I/O X for 1 pci (can only be used as clock then 2 alternate function) H pci_gnt_n[0] I/O Z pci_inta_n Output Z ...
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IDT 79RC32332 Reset Name Type State Status sdram_bemask_n Output H [3:0] sdram_245_oe_n Output H sdram_245_dt_r_n Output Z On-Chip Peripherals dma_ready_n[0] I/O Z pio[7:0] I/O See related pins uart_rx[0] I/O Z uart_tx[0] I/O Z spi_mosi I/O L spi_miso I/O Z spi_sck ...
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IDT 79RC32332 Reset Name Type State Status spi_ss_n I/O H CPU Core Specific Signals cpu_nmi_n Input cpu_masterclk Input cpu_int_n[1:0] Input cpu_coldreset_n Input L cpu_dt_r_n Output Z JTAG Interface Signals jtag_tck Input jtag_tdi, Input ejtag_dint_n jtag_tdo, Output Z ejtag_tpc jtag_tms Input ...
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IDT 79RC32332 Reset Name Type State Status ejtag_pcst[2:0] I/O Z ejtag_debugboot Input ejtag_tms Input Debug Signals debug_cpu_dma_n I/O Z debug_cpu_ack_n I/O Z debug_cpu_ads_n I/O Z debug_cpu_i_d_n I/O Z Drive Strength Capability Low EJTAG PC Trace Status Information 111 (STL) Pipe ...
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IDT 79RC32332 Logic Diagram — RC32332 cpu_masterclk cpu_coldreset_n cpu_nmi_n cpu_int_n[1:0] cpu_dt_r_n pci_cbe_n[3:0] pci_ad[31:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[0] pci_req_n[2] pci_gnt_n[0] pci_gnt_n[2] pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_mdo pci_eeprom_cs pci_eeprom_sk jtag_tck jtag_tms jtag_tdi jtag_tdo jtag_trst_n debug_cpu_dma_n ...
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IDT 79RC32332 Mode Bit Settings to Configure Controller on Reset The following table lists the mode bit settings to configure the controller on cold reset. Pin Mode Bit ejtag_pcst[2:0] 2:0 MSB (2) debug_cpu_i_d_n 3 debug_cpu_ack_n 4 debug_cpu_ads_n 5 debug_cpu_dma_n 6 ...
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IDT 79RC32332 pci_host_mode Settings During cold reset initialization, the RC32332’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU must configure the RC32332’s PCI configuration registers, including the read-only ...
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IDT 79RC32332 Reset Specification VCC cpu_masterclk (MClk) cpu_coldreset_n modebit[9:0] >= 110 ms 120 ms Figure 3 Mode Configuration Interface Cold Reset Sequence CRRise > May 4, 2004 ...
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IDT 79RC32332 AC Timing Characteristics — RC32332 Ta Commercial = 0°C to +70°C; Ta Industrial = -40°C to +85°C 3.3V version: V Core = +3.3V±5 2.5V version: V Core = +2.5V±5 Signal Symbol Local System Interface ...
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IDT 79RC32332 Signal Symbol pci_idsel, pci_req_n[2], Thld pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n pci_eeprom_mdi Tsu pci_eeprom_mdi Thld pci_eeprom_mdo, pci-eeprom_cs Tdo pci_eeprom_sk Tdo pci_ad[31:0], pci_cbe_n[3:0], Tdo pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n pci_req_n[0], pci_gnt_[2], Tdo pci_gnt_n[1], pci_gnt_n[0], pci_inta_n 3 PCI for ...
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IDT 79RC32332 Signal Symbol pci_ad[31:0], pci_cbe_n[3:0], Tdo pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n pci_req_n[0], pci_gnt_[2], Tdo pci_gnt_n[1], pci_gnt_n[0], pci_inta_n SDRAM Controller sdram_245_dt_r_n Tdo8 sdram_ras_n, sdram_cas_n, Tdo9 sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0], sdram_cke sdram_addr_12 Tdo10 sdram_245_oe_n Tdo11 sdram_245_dt_r_n Tdoh4 sdram_ras_n, ...
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IDT 79RC32332 Signal Symbol Reset mem_addr[19:17] Tsu10 mem_addr[19:17] Thld10 mem_addr[22:20] Tsu22 mem_addr[22:20] Thld22 Debug Interface debug_cpu_dma_n, Tsu20 debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] debug_cpu_dma_n, Thld20 debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] debug_cpu_dma_n, Tdo20 debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n debug_cpu_dma_n, Tdoh20 debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n JTAG Interface jtag_tms, ...
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IDT 79RC32332 — Standard EJTAG Timing Figure 4 represents the timing diagram for the EJTAG interface signals. The standard JTAG connector is a 10-pin connector providing 5 signals and 5 ground pins. For Standard EJTAG, a 24-pin connector has been ...
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IDT 79RC32332 Output Loading for AC Testing Note: PCI pins have been correlated to PCI 2.2. Recommended Operation Temperature and Supply Voltage 3.3V Device Grade Ambient Temperature Commercial 0°C to +70°C Ambient Industrial -40°C to +85°C Ambient 2.5V Device Grade ...
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IDT 79RC32332 DC Electrical Characteristics — RC32332 Ta Commercial = 0°C to +70°C; Ta Industrial = -40°C to +85°C 3.3V version: V Core = +3.3V±5 2.5V version: V Core = +2.5V±5 Parameter Minimum Input Pads V ...
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IDT 79RC32332 Power Consumption 3.3V Device Note: This table is based on a 2:1 pipeline-to-bus clock ratio. Parameter I Normal mode CC 1 Standby mode Power Normal mode Dissipation 1 Standby mode 1. RISCore 32300 CPU core enters Standby mode ...
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IDT 79RC32332 Power Curves The following four graphs contain the simulated power curves that show power consumption at various bus frequencies. Figures 6 and 7 apply to the 3.3V device, while Figures 8 and 9 apply to the 2.5V device. ...
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IDT 79RC32332 0.95 0.90 0.85 0.80 0.75 0.70 0.65 1.6 1.5 1.4 1.3 1.2 1.1 1 System Bus Speed (MHz) Figure 8 Typical Power Usage — RC32T332 Device 55 60 System Bus Speed (MHz) Figure 9 ...
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IDT 79RC32332 Absolute Maximum Ratings Symbol V Core cc 3.3V Device V Core cc 2.5V Device V I 3.3V Device Vi 2.5V Device Vimin Tstg 1. Functional and tested operating conditions are given in Table 7. Absolute maximum ...
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IDT 79RC32332 Pin Function Alt 20 mem_addr[ mem_addr[ mem_addr[ mem_addr[10 mem_addr[11 output_clk core cc 28 mem_addr_12 29 sdram_addr_12 30 sdram_cke 31 sdram_cs_n[2] 32 sdram_cs_n[3] 33 ...
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IDT 79RC32332 RC32332 Alternate Signal Functions Pin Alt #1 Alt #2 13 sdram_addr[2] 14 sdram_addr[3] 15 sdram_addr[4] 18 sdram_addr[5] 19 sdram_addr[6] 20 sdram_addr[7] 21 sdram_addr[8] 22 sdram_addr[9] 23 sdram_addr[10] 24 sdram_addr[11] 35 sdram_addr[13] 38 sdram_addr[14] 39 sdram_addr[15] Pin Alt #1 ...
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IDT 79RC32332 RC32332 Package Drawing — 208-pin PQFP May 4, 2004 ...
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IDT 79RC32332 RC32332 Package Drawing — Page Two May 4, 2004 ...
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IDT 79RC32332 Ordering Information 79RCXX V DDD Product Operating Device Type Voltage Type 332 V = 3.3V ± 2.5V ±5% 79RC32 = 32-bit family product Valid Combinations 3.3V Device 79RC32V332 - 100DH, 133DH, 150DH 79RC32V332 - 100DHI, 133DHI, ...