IDT79RC64T574-200DZ IDT, Integrated Device Technology Inc, IDT79RC64T574-200DZ Datasheet - Page 2

• Manufacturer Part Number: IDT79RC64T574-200DZ
• Description: IC MPU 64BIT EMB 200MHZ 128-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T574-200DZ

• Processor Type: RISC 64-Bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T574-200DZ

Device Overview
Device Overview
Device Overview
Device Overview
mance-critical embedded applications that include high-end internet-
working systems, digital set-top boxes, web browsers, color printers,
and graphics terminals.
RC4640/50 and RC64474/475 processors. This unprecedented upgrad-
ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1
range of floating-point; and 4:1 range of DSP performance in a single
socket.
operations, the RC64574/575 have been optimized for high-perfor-
mance applications through the integration of high-performance compu-
tational units and a high-performance memory hierarchy. The result is a
low-cost CPU that is capable of more than 330 Dhrystone MIPS.
Through the RC64574/64575 processors IDT offers:
RISCore4000/RISCore5000 Family of Socket Compatible Processors
RISCore4000/RISCore5000 Family of Socket Compatible Processors
RISCore4000/RISCore5000 Family of Socket Compatible Processors
RISCore4000/RISCore5000 Family of Socket Compatible Processors
79RC64574™ 79RC64575™
IDT’s 79RC64574/575 processors serve a wide range of
The RC64574/575 allow a socket compatible upgrade path for IDT’s
With special emphasis on system bandwidth, floating- point and DSP
1.
user’s manual.
Detailed system operation information is provided in the RC64574/RC64575
High-performance upgrade paths to existing embedded
customers in the internetworking, office automation and
visualization markets.
Significant floating-point performance improvements over
currently available, moderately priced MIPS CPUs.
Performance improvements through the use of the MIPS-IV ISA.
High-performance DSP acceleration
CPU
Performance
FPA
Caches
External Bus
Voltage
Frequencies
Packages
MMU
Key Features
64-bit RISCore4000 w/
DSP extensions
>350MIPS
89 mflops, single preci-
sion only
8kB/8kB, 2-way,
lockable by set
32-bit
3.3V
100-267 MHz
128 PQFP
Base-Bounds
Cache locking, on-chip
MAC, 32-bit external
bus
RC4640
32-bit External Bus Processors
1 1 1 1
128 QFP
64-bit RISCore4000
>330MIPS
125 mflops, single and
double precision
16kB/16kB, 2-way,
32-bit, Superset pin
compatible w/RC4640
3.3V
180-250 MHz
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-bit
external bus
lockable by set
RC64474
Table 1 RISCore4000/RISCore5000 Processor Family
64-bit RISCore5000 w/
DSP extensions
>330MIPS
666 mflops, single and
double precision
32kB/32kB, 2-way,
lockable by line
32-bit, Superset pin
compatible w/RC4640,
RC64474
2.5V
200-250 MHz
128 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-bit
external bus
perfor-
RC64574
2 of 28
Instruction Issue Mechanism
Instruction Issue Mechanism
Instruction Issue Mechanism
Instruction Issue Mechanism
machines that use a traditional 5-stage integer pipeline, as shown in the
pipeline diagram on Page 3. For multi-issue operations, these devices
recognize the following two general classes of instructions:
no data dependencies to restrict multi-issue performance. As they are
brought on-chip, these instruction classes are pre-decoded by the
RC64574/575, and the class information is then stored in the instruction
cache. Assuming there are no pending resource conflicts, the devices
can issue one instruction per class per pipeline clock cycle.
(for example, division or square root instructions) or integer unit (such as
multiply)—can restrict the issue of instructions. Note that these proces-
sors do not perform out-of-order or speculative execution; instead, the
pipeline slips until the required resource becomes available.
and the RC64574/575 fetch two instructions from the cache per cycle.
Thus, for optimal performance, compilers should attempt to align branch
targets to allow dual-issue on the first target cycle, because the instruc-
tion cache only performs aligned fetches.
The RC64574 and RC64575 are limited dual-issue super-scalar
Such a broad separation of instruction classes insure that there are
However, longer latency resources—in either the floating-point ALU
On dual-issue instruction pairs, there are no alignment restrictions,
64-bit RISCore4000 w/
DSP extensions
>350MIPS
89 mflops, single preci-
sion only
8kB/8kB, 2-way,
lockable by set
32- or 64-bit
3.3V
100-267 MHz
208 QFP
Base-Bounds
Cache locking, on-chip
MAC, 32-bit & 64 bit
bus option
Floating-point ALU
All others
RC4650
64-bit External Bus Processors
64-bit RISCore4000
>330MIPS
125 mflops, single and
double precision
16kB/16kB, 2-way,
lockable by set
32-or 64-bit, Superset
pin compatible w/
RC4650
3.3V
180-250 MHz
208 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
RC64475
64-bit RISCore5000 w/
DSP extensions
>330MIPS
666 mflops, single and
double precision
32kB/32kB, 2-way,
lockable by line
32-or 64-bit, Superset
pin compatible w/
RC4650, RC64475
2.5V
250 MHz
208 QFP
96 page TLB
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
December 14, 2001
RC64575