IDT79RC64T574-200DZ IDT, Integrated Device Technology Inc, IDT79RC64T574-200DZ Datasheet - Page 3

• Manufacturer Part Number: IDT79RC64T574-200DZ
• Description: IC MPU 64BIT EMB 200MHZ 128-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T574-200DZ

• Processor Type: RISC 64-Bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T574-200DZ

Instruction Set Architecture
Instruction Set Architecture
Instruction Set Architecture
Instruction Set Architecture
including CP1 and CP1X functional units and their instruction set. Both
32- and 64-bit data operations are performed by utilizing thirty-two
general purpose 64-bit registers (GPR) that are used for integer opera-
tions and address calculation. The complete on-chip floating-point co-
processor (CP1)—which includes a floating-point register file and execu-
tion units—forms a “seamless” interface, decoding and executing
instructions in parallel with the integer unit.
double precision arithmetic—as specified in the IEEE Standard 754—
and are separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported, and the multiplier is partially pipelined, allowing the initiation
of a new multiply instruction every fourth pipeline cycle. The floating-
point register file is made up of thirty-two 64-bit registers. The floating-
point unit can take advantage of the 64-bit wide data cache and issue a
co-processor load or store doubleword instruction in every cycle.
rated on-chip and provide the path through which the virtual memory
system’s page mapping is examined and changed, exceptions are
handled, and any operating mode selections are controlled. A secure
user processing environment is provided through the user, supervisor,
and kernel operating modes of virtual addressing to system software.
Bits in a status register determine which of these modes is used.
Integer Pipeline
Integer Pipeline
Integer Pipeline
Integer Pipeline
pipeline clocks—as follows:
the speed of the multiplier unit, a “fast multiply” disable reset mode bit
(see Table 2) is featured. When this bit is asserted, each multiply opera-
tion shown in Table 1 has its latency and repeat rate increased by one
cycle.
79RC64574™ 79RC64575™
The RC64574/575 implement a superset of the MIPS-IV 64-bit ISA,
The system control coprocessor (CP0) registers are also incorpo-
The integer instruction execution speed is tabulated—in number of
To insure that the maximum frequency of operation is not limited by
CP1’s floating-point execution units support both single and
Load
Store
MULT/MULTU
DMULT/DMULTU
DIV/DIVU
DDIV/DDIVU
MAD/MADU
MSUB/MSUBU
Other Integer ALU
Branch
Jump
Operation
Table 2 Integer Instruction Execution Speed
2
2
4
6
36
68
3
4
1
2
2
Latency
1
1
3
5
36
68
2
3
1
2
2
Repeat
3 of 28
RC64574/575, and the caches contain special logic that will allow any
combination of loads and stores to execute in back-to-back cycles
without requiring pipeline slips or stalls, assuming the operation does
not miss in the cache.
Computational Units
Computational Units
Computational Units
Computational Units
logic unit (ALU), for Integer ALU functions other than multiply and
divide. Bypassing is used to support back-to-back ALU operations at the
full pipeline rate, without requiring stalls for data dependencies.
operations, the Integer Multiply/Divide unit of the RC64574/ 575 is
separated from the primary ALU. The pipeline stalls only if an attempt to
access the HI or LO registers is made before an operation completes.
ALU operations—other than DIV/SQRT operations—and is pipelined to
allow a single-cycle repeat rate for single-precision operations.
point ALU, to ensure that these longer latency operations do not prevent
the issue of other floating-point operations. Separate logical units are
also provided on the RC64574/575 to implement load, store, and branch
operations.
fused multiply-adds, multiply-subtracts and three operand multiply oper-
ations, new instructions have been added over and above the MIPS-IV
ISA.
System Interfaces
System Interfaces
System Interfaces
System Interfaces
bus compatible with the RC4650 and RC64475 system interface. The
system interface consists of a 64-bit Address/Data bus with eight parity-
check bits and a 9-bit command bus.
transfers are protected with an 8-bit parity check bus, SysADC. When
initialized for 32-bit operation, the RC64575’s SysAD can be viewed as a
32-bit multiplexed bus that is protected by four parity-check bits.
bus compatible with the RC4640 and RC64474. During 32-bit operation,
SysAD transfers are performed on a 32-bit multiplexed bus (SysAD
31:0) that is protected by 4 parity check bits (SysADC 6:0).
backs, stores to uncached or write-through addresses—use the on-chip
write buffer. The write buffer holds a maximum of four 64-bit addresses
and 64-bit data pairs. The entire buffer is used for a data cache write-
back and allows the processor to proceed in parallel with memory
updates.
RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, and ValidIn*; six inter-
rupt inputs, and a simple timing specification that is capable of trans-
Load and branch latencies are minimized by the short pipeline of the
The RC64574/575 implement a full, single-cycle 64-bit arithmetic
To allow the longer latency operations to run in parallel with other
The Floating-point ALU unit is responsible for all of the CP1/CP1X
The Floating-point DIV/SQRT unit is separated from the floating-
Intended to enhance the performance of DSP algorithms such as fast
The RC64575 supports a 64-bit system interface that is pin and
During 64-bit operation, RC64575 system address/data (SysAD)
Writes to external memory—whether they are cache miss write-
Included in the system interface are six handshake signals:
The RC64574 supports a 32-bit system interface that is pin and
December 14, 2001