A80960KB20 Intel, A80960KB20 Datasheet - Page 16

• Manufacturer Part Number: A80960KB20
• Description: IC MPU I960KB 20MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80960KB20

• Processor Type: i960
• Features: KB suffix, 32-Bit, 512 Byte Cache
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: i960
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803516

80960KB
2.0
2.1
The 80960KB is implemented in CHMOS IV
technology and therefore has modest power require-
ments. Its high clock frequency and numerous
output buffers (address/data, control, error and
arbitration signals) can cause power surges as
multiple output buffers simultaneously drive new
signal levels. For clean on-chip power distribution,
V
functional units. Power and ground connections
10
CC
FAILURE
IAC/INT
INT
INT
INT
N.C.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
NAME
1
2
3
and V
/INTR
/INTA
ELECTRICAL SPECIFICATIONS
Power and Grounding
0
SS
pins separately feed the device’s
TYPE
O.D.
O.D.
N/A
I/O
O
Table 5. 80960KB Pin Description: Support Signals (Sheet 2 of 2)
I
I
I
INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
After RESET deasserts and before the first bus transaction begins, FAILURE
asserts while the processor performs a self-test. If the self-test completes
successfully, then FAILURE deasserts. The processor then performs a zero
checksum on the first eight words of memory. If it fails, FAILURE asserts for a
second time and remains asserted. If it passes, system initialization continues
and FAILURE remains deasserted.
INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines
how the signal is interpreted. To signal an interrupt or IAC request in a
synchronous system, this pin — as well as the other interrupt pins — must be
enabled by being deasserted for at least one bus cycle and then asserted for at
least one additional bus cycle. In an asynchronous system the pin must remain
deasserted for at least two bus cycles and then asserted for at least two more bus
cycles.
During system reset, this signal must be in the logic high condition to enable
normal processor operation. The logic low condition is reserved.
INTERRUPT 1, like INT
INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. If INT
INT
interrupt controller.
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. If INT
the INT
interrupt-acknowledge transactions. The INTA output is latched on-chip and
remains valid during T
NOT CONNECTED indicates pins should not be connected. Never connect any
pin marked N.C. as these pins may be reserved for factory use.
1
pins. If INTR, it is used to receive an interrupt request from an external
0
, INT1 and INT2 pins. If INTA, it is used as an output to control
d
0
cycles; as an output, it is open-drain.
, provides direct interrupt signaling.
must be made to all 80960KB power and ground
pins. On the circuit board, all V
strapped closely together, preferably on a power
plane; all V
preferably on a ground plane.
2.2
Place a liberal amount of decoupling capacitance
near the 80960KB. When driving the L-bus the
processor can cause transient power surges, partic-
ularly when connected to a large capacitive load.
2
DESCRIPTION
, it has the same interpretation as the INT
Power Decoupling
Recommendations
ss
3
, it has the same interpretation as
pins should be strapped together,
cc
pins must be
0
and