TS68040VR25A Atmel, TS68040VR25A Datasheet

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... The Use of the TS88915T Clock Driver is Suggested Description The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32- bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device single chip, the TS68040 ...

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R suffix PGA 179 Ceramic Pin Grid Array Cavity Down Figure 1. Block Diagram CONVERT EXECUTE WRITE BACK FLOATING- POINT UNIT TS68040 2 INSTRUCTION DATA BUS INSTRUCTION ATC INSTRUCTION INSTRUCTION MMU/CACHE/SNOOP FETCH CONTROLLER INSTRUCTION MEMORY UNIT DECODE EFFECTIVE ADDRESS CALCULATE ...

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Introduction 2116A–HIREL–09/02 The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte- ger unit processing capabilities of the TS68030 microprocessor with independent 4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the 32-bit registers ...

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Pin Assignments PGA 179 Figure 2. Bottom View Table 1. Power Supply Affectation to PGA Body GND PLL Internal Logic C6, C7, C9, C11,C13, K3, K16, L3, M16, R4, R11, R13, S10, T4, S9, R6, R10 Output Drivers B2, B4, ...

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CQFP 196 Figure 3. Pin Assignments Table 2. Power Supply Affectation to CQFP Body GND PLL Internal Logic 4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124, 125, 129, 130, 141, 159, 172 Output Drivers 7, ...

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Signal Description Figure 4. Functional Signal Groups TS68040 6 Figure 4 and Table 3 describe the signals on the TS68040 and indicate signal functions. The test signals, TRST, TMS, TCK, TDI, and TDO, comply with subset P-1149.1 of the IEEE ...

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Table 3. Signal Index Signal Name Mnemonic Address Bus Data Bus Transfer Type Transfer Modifier TM2, TM0 Transfer Line Number TLN1, TLN0 User Programmable Attributes Read Write Transfer Size SIZ1, SIZ0 Bus Lock Bus Lock End Cache Inhibit Out Transfer ...

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... Power supply CC GND Ground connection This drawing describes the specific requirements for the microprocessor TS68040 - 25 MHz and 33 MHz, in compliance with MIL-STD-883 class B or Atmel standard screening. 1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-I-38535: general specifications for microcircuits. 3. DESC 5962-93143. The microcircuits are in accordance with the applicable document and as specified herein ...

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Electrical Characteristics Absolute Maximum Ratings Table 4. Absolute Maximum Ratings Symbol Parameter V Supply Voltage Range CC V Input Voltage Range I P Power Dissipation D T Operating Temperature C T Storage Temperature Range stg T Junction Temperature J T ...

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Thermal Considerations General Thermal Considerations Thermal Device Characteristics Die and Package Power Considerations TS68040 10 This section is only given as user information. As microprocessors are becoming more complex and requiring more power, the need to efficiently cool the device ...

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Output Buffer Mode 2116A–HIREL–09/02 The 68040 is capable of resetting to enable for a combination of either large buffers or small buffers on the outputs of the miscellaneous control signals, data bus, and address bus/transfer attribute pins. The large buffers ...

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Relationships Between Thermal Resistances and Temperatures Thermal Management Techniques TS68040 12 To calculate the specific power dissipation of a specific design, the termination method of each signal must be considered. For example, a signal output that is not connected would ...

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Thermal Characteristics in Still Air Table 7. Thermal Parameters With No Heat Sink or Air-flow Defined Parameters Watts 125°C 5 Watts 125°C Thermal Characteristics in Forced Air Table 8. Thermal Parameters With Forced Air Flow ...

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Thermal Characteristics with a Heat Sink TS68040 14 By reviewing the maximum ambient operating temperatures, it can be seen that by using the all-small-buffer configuration of the TS68040 with a relatively small amount of air flow (100 LFM), a 0-70°C ...

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All pin fin heat sinks tested were made from extrusion Al products. The planar face of the heat sink mating to the package should have a good degree of planarity has any curvature, the curvature should be ...

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Table 9. Thermal Parameters With Heat Sink and No Air Flow Thermal Mgmt. Technique Defined Parameters Heat Sink P D 2338B 3W 2338B 5W Thermal Characteristics with a Heat Sink and Forced Air Table 10. Thermal Parameters with Heat Sink ...

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... Thermal Resistance Junction-to-case The microcircuits shall meet all mechanical environmental requirements of either MIL- STD-883 for class B devices or for Atmel standard screening. The document where are defined the marking are identified in the related reference doc- uments. Each microcircuit are legible and permanently marked with the following information as minimum: • ...

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Quality Conformance Inspection DESC/MIL-STD-883 Electrical Characteristics General Requirements Static Characteristics Table 12. Electrical Characteristics -55° 4.75V V 5.25V unless otherwise specified C Jmax CC Symbol Characteristic V Input High Voltage IH V Input Low Voltage IL V ...

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Table 12. Electrical Characteristics (Continued) -55° 4.75V V 5.25V unless otherwise specified C Jmax CC Symbol Characteristic V Output Low Voltage OL Larger buffers - I OL Small buffers - Power Dissipation (T D ...

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Table 14. Output AC Timing Specifications These output specifications are only for 25 MHz. They must be scaled for lower operating frequencies. Refer to TS6804DH/AD for further information. -55°C T Num Characteristic 11 BCLK to address CIOUT, LOCK, LOCKE, R/W, ...

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Notes: 1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 transmission line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50 to 2.5V. ...

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Table 15. Input AC Timing Specifications (Figure 9 to Figure 15) (Continued) -55° 4.75V V 5.25V unless otherwise specified C Jmax CC Num Characteristic 44c TTn Valid to BCLK (Setup) 44d R/W Valid to BCLK (Setup) 44e ...

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Table 16. JTAG Timing Application (Figure 16 to Figure 19) -55° max; 4.75V V 5.25V unless otherwise specified Num Characteristic TCK Frequency 1 TCK Cycle Time 2 TCK Clock Pulse Width Measured at 1.5V 3 ...

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Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified. 2. Maximum operating junction temperature (T tested +125°. Testing is performed by setting the junction temperature T C temperatures to rise and fall ...

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Figure 11. DLE Timing Burst Access Figure 12. Bus Arbitration Timing TS68040 25 ...

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Figure 13. Snoop Hit Timing TS68040 26 2116A–HIREL–09/02 ...

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Figure 14. Snoop Miss Timing Figure 15. Other Signal Timing TS68040 27 ...

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TS68040 28 Figure 16. Clock Input Timing Diagram Figure 17. TRST Timing Diagram Figure 18. Boundary Scan Timing Diagram 2116A–HIREL–09/02 ...

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Functional Description Programming Model 2116A–HIREL–09/02 Figure 19. Test Access Port Timing Diagram The TS68040 integrates the functions of the integer unit, MMU, and FPU. As shown in Figure 20, the registers depicted in the programming model provide access and control ...

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TS68040 30 registers may be used for word and long-word operations, and all of the 16 general-pur- pose registers (D0-D7, A0-A7 in Figure 20) may be used as index registers. The eight, 80-bit, floating-point data registers (FP0-FP7) are analogous to ...

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For the subset of the FPU instructions that generate exception traps, the 32-bit floating- point instruction address register (FPIAR) is loaded with the logical address of an instruction before the instruction is executed. This address can then be used ...

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Data Types and Addressing Modes Table 18. Data Types Operand Data Type Bit Bit Field BCD Byte Integer Word Integer Long-word Integer Quad-word Integer 16-byte Single-precision Real Double-precision Real Extended-precision Real Note Integer Unit. TS68040 32 The ...

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Table 19. Addressing Modes Addressing Modes Register Direct Date Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect With Postincrement Address Register Indirect With Predecrement Address Register Indirect With Displacement Register Indirect With Index Address Register ...

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TS68040 34 The instruction provided by the TS68040 are listed in Table 20. The instruction set has been tailored to support high-level languages and is optimized for those instructions most commonly executed (however, all instructions listed are fully supported). Many ...

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Table 20. Instruction Set Summary (Continued) Mnemonic Description ILLEGAL Take Illegal Instruction Trap JMP Jump JSR Jump To Subroutine LEA Load Effective Address LINK Link And Allocate LSL, LSR Logical Shift Left And Right MOVE Move (1) MOVE16 16-byte ...

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TS68040 36 Table 20. Instruction Set Summary (Continued) Mnemonic Description SBCD Substract Decimal With Extend Scc Set Conditionally STOP Stop SUB Subtract SUBA Subtract Address SUBI Subtract Immediate SUBQ Subtract Quick SUBX Subtract With Extend SWAP Swap Register Words TAS ...

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Instruction and Data Caches Cache Organization 2116A–HIREL–09/02 Studies have shown that typical programs spend much of their execution time in a few main routines or tight loops. Earlier members of the TS68000 Family took advantage of this locality of reference ...

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Figure 21. Cache Organization Overview TS68040 38 The caches are accessed by physical addresses from the on-chip MMUs. The transla- tion of the upper bits of the logical address occurs concurrently with the accesses into the set array in the ...

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Cache Coherency Cache Instructions Operand Transfer Mechanisms Transfer Types Burst Transfer Operation Bus Snooping 2116A–HIREL–09/02 Cachability of data in each memory page is controlled by two bits in the page descriptor for each page. Cachable pages may be either write ...

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Exception Processing Memory Management Units Translation Mechanism TS68040 40 The TS68040 provides the same extensions to the exception stacking process as the TS68030. If the M bit in the status register is set, the master stack pointer is used for ...

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Address Translation Cache Translation Tables 2116A–HIREL–09/02 An integral part of the translation function previously described is the dual cache mem- ory that stores recently used logical-to-physical address translation information (page descriptors) for instruction and date accesses. These caches are 64-entry, ...

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... Microcircuits are prepared for delivery in accordance with MIL-M-38510 or Atmel standard. Atmel offers a certificate of compliances with each shipment of parts, affirming the prod- ucts are in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not tested at temperature extremes for the entire temperature range. ...

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Package Mechanical Data 179 pins – PGA 2116A–HIREL–09/02 Millimeters Dim Min Max A 46.863 47.625 B 46.863 47.625 C 2.3876 1.875 D 4.318 4.826 E 1.143 1.4 F 1.143 1.4 G 2.54 BSC (1) H 0.432 0.483 Note: 1. For ...

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Tie Bar CQFP Cavity Up (on request) TS68040 44 Dim Millimeters A 3.30 max B 0.23 +0.05 0.23 -0.038 C 0.635 typ. D1 33.91 ± 0.25 J 0.89 ± 0.13 L 63.5 ± 0.51 Inches 0.130 max ...

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Gullwing CQFP cavity up * Reduce pin count shown for clarity, 49 pins per side 2116A–HIREL–09/02 Symbol Millimeters A 4.19 max A1 0.673 ± 0.2 0.23 +0.05 b 0.23 -0.038 0.127 +0.05 c 0.127 -0.025 D/E 33.91 ...

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Ordering Information MIL-STD-883 C and Internal Standard Device Temperature range -55 +125° -40 +110°C Package: Standard lead finish F: CQFP/Gullwing leads R: PGA FT: CQFP Flat tie-bar (3) Notes: 1. ...

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... C J CQFP 196 T = -55/+T = +125 C J TS68040 Frequency (MHz) Drawing number 25 Atmel datasheet 33 Atmel datasheet 25 Atmel datasheet 33 Atmel datasheet 25 5962-9314301MXA 33 5962-9314302MXA 25 5962-9314301MXC 33 5962-9314302MXC 25 5962-9314301MYC 33 5962-9314302MYC 25 5962-9314301MZA 25 5962-9314301MZC 33 5962-9314302MZA 33 5962-9314302MZC 25 Atmel datasheet 33 Atmel datasheet 25 Atmel datasheet 33 Atmel datasheet 25 Atmel datasheet 33 Atmel datasheet 47 ...

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... Standard Product Commercial Atmel Part Number Norms TS68040VR25A Atmel standard TS68040VR33A Atmel standard TS68040MR25A Atmel standard TS68040MR33A Atmel standard TS68040VF25A Atmel standard TS68040VF33A Atmel standard TS68040MF25A Atmel standard TS68040MF33A Atmel standard Note: FT: available on request. TS68040 48 Package Temperature Range (°C) PGA 179 ...

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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...