NS486SXL-25 National Semiconductor, NS486SXL-25 Datasheet - Page 8

• Manufacturer Part Number: NS486SXL-25
• Description: IC NS486SXL 132PQFP
• Manufacturer: National Semiconductor

Specifications of NS486SXL-25

• Processor Type: 486SX
• Speed: 25MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS486SXL-25

SA 25 0
SD 15 0
BHE
IOR
IOW
MEMR
MEMW
CS16
RDY
DRQ6 DRQ4
DRQ2 DRQ0
DACK6 DACK4
DACK2 DACK0
TC EOP
Symbol
2 0 Pin Description Tables
Symbol
Pins
26
16
1
1
1
1
1
1
1
Type
Pins
I O
4
4
1
O
O
O
O
O
O
I
I
Type
System Address bus These output-only signals carry the latched address for the current access
DRAM accesses multiplex the row and column addresses for the DRAMs on the SA 12 1 pins During
Interrupt Acknowledge cycles the internal master interrupt controller’s cascade line signals CAS 2 0
are driven onto SA 25 23 respectively
System Data bus This bi-directional data bus provides the data path for all memory and I O accesses
During transfers with 8-bit devices the upper data byte is not used (SD 15 8 )
Byte High Enable This active-low signal indicates that the high byte (odd address byte) is being
transferred External 16-bit devices should use this signal to help them determine that a data byte is to
be transferred on the upper byte or the System Data bus (SD 15 8 )
IO Read command This active-low signal instructs an I O device to place data onto the system data
bus
IO Write command This active-low signal indicates to an I O device that a write operation is in process
on the system bus
MEMory Read command This active-low signal instructs a memory mapped device to place data onto
the system data bus
MEMory Write command This active-low signal indicates to a memory mapped device that a write
operation is in process on the system bus
Chip Select 16-bit This active-low feedback signal indicates that the device being accessed is a 16-bit
device This signal should be driven by external devices with an open collector or TRI-STATE driver
ReaDY An external device may drive this signal inactive low to insert wait states and extend the
external bus cycle This signal should be driven with an open collector be TRI-STATE driven
I O
O
I
DMA ReQuest A DRQn signal requests the internal DMA Controller to transfer data between
the Requesting Device and memory
DMA ACKnowledge When the CPU has relinquished control of the bus to a requesting DMA
channel the appropriate active-low DACKn signal acknowledges the winning DRQn
Terminal Count End Of Process This signal may operate either as a terminal count output or an
active-low End of Process input As TC an active-high pulse occurs on this signal when the
terminal count for any DMA channel has been reached As EOP an external device may
terminate the DMA transfer by driving this signal active-low
(Continued)
TABLE 2-1 Bus Interface Unit Pins
TABLE 2-2 DMA Control Pin
8
Function
Function