IDTSTAC9228D3TAEA2XR IDT, Integrated Device Technology Inc, IDTSTAC9228D3TAEA2XR Datasheet - Page 30

• Manufacturer Part Number: IDTSTAC9228D3TAEA2XR
• Description: IC AUDIO CODEC 8CH HD 3.3V 48QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec, HDr

Specifications of IDTSTAC9228D3TAEA2XR

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 3 / 4
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 105
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 3.8 V ~ 4.2 V; 4.28 V ~ 4.73 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9228D3TAEA2XR

IDT™
STAC9227/9228/9228D
8-CHANNEL HIGH DEFINITION AUDIO CODEC
8-CHANNEL HIGH DEFINITION AUDIO CODEC
carry individual channels of digital microphone data to the STAC927x family. In the event that a sin-
gle microphone is used, the data is routed to both ADC channels.
The DMIC_CLK output is programmable from 1.176 MHz to 4.704 MHz in 1.176 MHz increments,
and is synchronous to the 24 MHz internal clock. The default frequency is 2.352 MHz.
The STAC927x family supports the following digital microphone configurations:
Digital Mics Date Sample ADC Conn.
Power
D0-D3
State
D0
D1
D2
D3
0
1
2
3
4
DMIC Widget
Enabled?
Yes
Yes
Yes
Yes
No
pin and Single
second DMIC
on one DMIC
Double Edge
DMIC_0 or 1
Double Edge
Double Edge
Single Edge
Single Edge
Edge on the
Table 3. DMIC_CLK, DMIC_0 and DMIC_1 Operation During Power States
on DMIC_0
on either
and 1
N/A
pin.
OR
Clock Disabled Input Disabled DMIC_CLK Remains Low
Clock Disabled Input Disabled DMIC_CLK Remains Low
Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down
Clock Capable Input Capable
Clock Capable Input Capable
DMIC_CLK
Output
Table 2. Valid Digital Microphone Configurations
0, 1, or 2
0, 1, or 2
0, 1, or 2
0, 1, or 2
IDT CONFIDENTIAL
N/A
30
DMIC_0,1
No Digital Microphones
Available on either DMIC_0 or DMIC_1
Both ADC Channels produce data, may be in phase or out by 1/2
DMIC_CLK period depending upon external configuration and
timing
Available on either DMIC_0 or DMIC_1, External logic required to
support sampling on a single Digital Mic pin channel on rising
edge and second Digital Mic right channel on falling edge of
DMIC_CLK for those digital microphones that don’t support
alternative clock edge capability. If both DMIC_0 and DMIC_1 are
used to support 2 digital microphones, 2 separate ADC units will
be used, however, this configuration is not recommended since it
consumes two stereo ADC resources.
Requires both DMIC_0 or DMIC_1, External logic required to
support sampling on a single Digital Mic pin channel on rising
edge and second Digital Mic right channel on falling edge of
DMIC_CLK for those digital microphones that don’t support
alternative clock edge capability. Two ADC units are required to
support this configuration
Connected to DMIC_0 and DMIC_1, External logic required to
support sampling on a single Digital Mic pin channel on rising
edge and second Digital Mic right channel on falling edge of
DMIC_CLK for those digital microphones that don’t support
alternative clock edge capability. Two ADC units are required to
support this configuration
DMIC_CLK Output is Enabled when either DMIC_0
or DMIC_1 Input Widget is Enabled. Otherwise, the
DMIC_CLK remains Low
DMIC_CLK Output is Enabled when either DMIC_0
or DMIC_1 Input Widget is Enabled. Otherwise, the
DMIC_CLK remains Low
STAC9227/9228/9228D
Notes
Notes
PC AUDIO
V 1.1 01/08