IDT821054APFG8 IDT, Integrated Device Technology Inc, IDT821054APFG8 Datasheet - Page 7

• Manufacturer Part Number: IDT821054APFG8
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APFG8

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 821054APFG8

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
1
SO1_(1-4)
SO2_(1-4)
SB1_(1-4)
SB2_(1-4)
SB3_(1-4)
VOUT1-4
SI1_(1-4)
SI2_(1-4)
VDDA12
VDDA34
GNDA1
GNDA2
GNDA3
GNDA4
VIN1-4
GNDD
VDDD
VDDB
BCLK
Name
CNF
DX1
DX2
DR1
DR2
FS
PIN DESCRIPTION
Ground
Ground
Power
Power
Power
Type
I/O
−
O
O
O
O
I
I
I
I
I
I
49, 55, 58, 64
51, 53, 60, 62
36, 47, 2, 13
35, 48, 1, 14
39, 44, 5, 10
38, 45, 4, 11
37, 46, 3, 12
Pin Number
41, 42, 7, 8
40, 43, 6, 9
50
54
59
63
21
52
61
24
57
56
26
29
27
30
31
32
Analog Ground.
All ground pins should be connected together.
Digital Ground.
All digital signals are referred to this pin.
+5 V Analog Power Supply.
These pins should be connected to ground via a 0.1
connected together.
+5 V Digital Power Supply.
+5 V Analog Power Supply.
This pin should be connected to ground via a 0.1
together.
Capacitor Noise Filter.
This pin should be connected to ground via a 0.22
Analog Voice Inputs of Channel 1-4.
These pins should be connected to the corresponding SLIC via a 0.22
Voice Frequency Receiver Outputs of Channel 1-4.
These pins can drive 300 Ω AC load. It can drive transformers directly.
SLIC Signalling Inputs with debounce function for Channel 1-4.
Bi-directional SLIC Signalling I/Os for Channel 1-4.
These pins can be individually programmed as input or output.
SLIC Signalling Outputs for Channel 1-4.
Transmit PCM Data Output, PCM Highway One.
Transmit PCM Data to PCM highway one. The PCM data is output through DX1 or DX2 as selected by
local register LREG5. This pin remains in high-impedance state until a pulse appears on the FS pin.
Transmit PCM Data Output, PCM Highway Two.
Transmit PCM Data to PCM highway two. The PCM data is output thought DX1 or DX2 as selected by
local register LREG5. This pin remains in high-impedance state until a pulse appears on the FS pin.
Receive PCM Data Input, PCM Highway One.
The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is
selected by local register LREG6.
Receive PCM Data Input, PCM Highway Two.
The PCM data is received from PCM highway one (DR1) or two (DR2). The receive PCM highway is
selected by local register LREG6.
Frame Synchronization.
FS is an 8 kHz synchronization clock that identifies the beginning of the PCM frame.
Bit Clock.
This pin clocks out the PCM data to DX1 or DX2 pin and clocks in PCM data from DR1 or DR2 pin. It may
vary from 512 kHz to 8.192 MHz and should be synchronous to FS.
7
Description
µ
F capacitor. All power supply pins should be connected
µ
F capacitor.
µ
F capacitor. All power supply pins should be
µ
INDUSTRIAL TEMPERATURE
F capacitor.