IDT821054APFG8 IDT, Integrated Device Technology Inc, IDT821054APFG8 Datasheet - Page 9

• Manufacturer Part Number: IDT821054APFG8
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APFG8

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 821054APFG8

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
2
filters. It provides a four-wire solution for the subscriber line circuitry in
digital switches. The IDT821054A converts analog voice signals to
digital PCM samples and digital PCM samples back to analog voice
signals. The digital filters are used to bandlimit the voice signals during
conversion.
Converters (ADC) and Digital-to-Analog Converters (DAC) in the
IDT821054A provide the required conversion accuracy. The associated
decimation and interpolation filtering is performed by both dedicated
hardware and Digital Signal Processor (DSP). The DSP also handles all
other necessary procession such as PCM bandpass filtering, sample
rate conversion and PCM companding.
2.1
device to control the IDT821054A. Two PCM buses are provided to
transfer the digital voice data.
2.1.1
The IDT821054A is a four-channel PCM CODEC with on-chip digital
A serial Microprocessor Interface (MPI) is provided for the master
The internal configuration registers (local/global), the SLIC signaling
CCLK
CCLK
CO
CS
CI
CO
CS
CI
FUNCTIONAL DESCRIPTION
MPI/PCM INTERFACE
MICROPROCESSOR INTERFACE (MPI)
High
High 'Z'
High 'Z'
performance
7
7
6
6
5
5
Command Byte
Command Byte
Figure - 2 An Example of the MPI Interface Read Operation (ID = 81H)
4
4
oversampling
Figure - 1 An Example of the MPI Interface Write Operation
3
3
2
2
1
1
Analog-to-Digital
0
0
'1'
7
'0'
6
'0'
5
Identification Code
9
Ignored
Data Byte 1
interface and the Coefficient-RAM of the IDT821054A are programmed
by the master device via MPI, which consists of four lines (pins): CCLK,
CS, CI and CO. All commands and data are aligned in byte (8 bits) and
transferred via the MPI interface. CCLK is the clock of the MPI interface.
The frequency of CCLK can be up to 8.192 MHz. CS is the chip
selection pin. A low level on CS enables the MPI interface. CI and CO
are data input and data output pins, carrying control commands and
data bytes to/from the IDT821054A.
of CI is latched on the rising edges of CCLK, while CO changes on the
falling edges of CCLK. The CCLK signal is the only reference of CI and
CO pins. Its duty and frequency may not necessarily be standard.
on the CI pin as command and the rest as data. To write another
command, the CS pin must be changed from low to high to finish the
previous command and then changed from high to low to indicate the
start of a new command. When a read/write operation is completed, the
CS pin must be set to high in 8-bit time.
byte(s), the IDT821054A will not accept any new commands from the CI
pin. But the data transfer sequence can be interrupted by setting the CS
pin to high at any time. See
MPI write and read operation timing diagrams.
'0'
4
The data transfer is synchronized to the CCLK signal. The contents
When the CS pin becomes low, the IDT821054A treats the first byte
During the execution of commands that are followed by output data
'0'
3
'0'
2
'0'
1
'1'
0
7
7
Figure - 1
6
6
5
5
INDUSTRIAL TEMPERATURE
Data Byte 1
Data Byte 2
and
4
4
Figure - 2
3
3
2
2
1
1
for examples of
0
0