EMC6D103S-CZC-TR SMSC, EMC6D103S-CZC-TR Datasheet - Page 80

• Manufacturer Part Number: EMC6D103S-CZC-TR
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC6D103S-CZC-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision 0.3 (03-01-07)
8.2.32
Register
Address
82h
/Write
Read
R/W
Notes:
Register 82h: Interrupt Enable 3 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP),
which is used to enable thermal events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] TEMP. Group temperature enable bit.
0=Out-of-limit temperature readings do not affect the state of the INT# pin (default)
1=Enable out-of-limit temperature readings to make the INT# pin active low
Bit[1] Ambient Temperature Status Enable bit.
Bit[2] Remote Diode 1 Temperature Status Enable bit.
Bit[3] Remote Diode 2 Temperature Status Enable bit
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual thermal error event bits are defined as follows:
0=disable
1=enable.
See
Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]
Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
All TACH inputs must be associated with a PWM output. If the tach is not being driven by the
associated PWM output it should be configured to operate in Mode 1 and the associated TACH
interrupt must be disabled.
Figure 6.1 Interrupt Controlon page
Interrupt Enable 3 (Temp)
Register
Table 8.53 Register 82h: Interrupt Enable 3 Register
Name
00
01
10
11
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Table 8.52 Bit Combinations
DATASHEET
(MSb)
Bit 7
RES
26.
80
Bit 6
RES
PWM Associated With Tachx
Bit 5
RES
Bit 4
RES
Reserved
PWM1
PWM2
PWM3
D2EN
Bit 3
D1EN
Bit 2
Bit 1
AMB
SMSC EMC6D103
TEMP
(LSb)
Bit 0
Datasheet
Default
Value
0Eh