EMC6D103-CZC SMSC, EMC6D103-CZC Datasheet
EMC6D103-CZC
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EMC6D103-CZC Summary of contents
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... Two low power modes when monitoring if off: Sleep and Shutdown EMC6D103-CZC FOR 24 PIN, SSOP LEAD-FREE ROHS COMPLIANT PACKAGE EMC6D103-CZC-TR FOR 24 PIN, SSOP LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL) SMSC EMC6D103 EMC6D103 Fan Control Device with High Frequency PWM ...
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... TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 2 DATASHEET Datasheet SMSC EMC6D103 ...
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... Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.8 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.10 SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 6 Hardware Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Input Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Resetting the EMC6D103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.2 Soft Reset (Initialization 6.3 Monitoring Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3.1 Continuous Monitoring Mode 6.3.2 Cycle Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 ...
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... Registers 94h-96h: PWMx Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.42 Register 97h: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.2.43 Register 98h:SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.2.44 Register FFh: SMSC Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 4 DATASHEET Datasheet SMSC EMC6D103 ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Chapter 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.1 PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.2 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Chapter 10 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Appendix A ADC Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Appendix B Example Fan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SMSC EMC6D103 5 DATASHEET Revision 0.3 (03-01-07) ...
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... List of Figures Figure 2.1 EMC6D103 24 Pin SSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5.1 Address Selection on EMC6D103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6.1 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7.1 Automatic Fan Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 7.2 Automatic Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 7.3 Spin Up Reduction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 7.4 Illustration of PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 7 ...
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... Table 8.34 Registers 64-66h: Minimum PWM Duty Cycle Table 8.35 PWM Duty vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 8.36 Registers 67-69h: Zone Low Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 8.37 Temperature Limit vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 8.38 egisters 6A-6Ch: Absolute Temperature Limit Table 8.39 Absolute Limit vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SMSC EMC6D103 7 DATASHEET Revision 0.3 (03-01-07) ...
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... Table 9.1 Timing for PWM[1:3] Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 9.2 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 10.1 24-Pin SSOP Package Parameters Table A.1 Analog-to-Digital Voltage Conversions for Hardware Monitoring Block Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 8 DATASHEET Datasheet SMSC EMC6D103 ...
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... The sampling and conversion of each voltage and temperature reading is performed once every monitoring cycle. (This is a power saving mode.) The EMC6D103 can be placed in one of two low-power modes: Sleep mode or Shutdown mode. These modes do not reset any of the registers of the device. In Sleep mode bias currents are on and the internal oscillator is on, but the the A/D converter and monitoring cycle are turned off ...
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... SCLK 3 VSS 4 VCC 5 VID0 6 VID1 7 VID2 8 VID3 9 TACH3/INT# 10 PWM2/INT# 11 TACH1 12 TACH2 Figure 2.1 EMC6D103 24 Pin SSOP Pinout Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features EMC6D103 DATASHEET Datasheet PWM1/xTest Out Vccp 2.5V 12V ...
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... A/D. 20 +5V_IN Analog input for +5V 22 +2.5V_IN Analog input for +2.5V 23 Vccp Analog input for +Vccp (processor voltage 3.0V). 21 12V_IN Analog input for +12V SMSC EMC6D103 Table 3.1 Pin Description BUFFER FUNCTION TYPE HARDWARE MONITORING BLOCK (24) I OD3 ...
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... FUNCTION TYPE HARDWARE MONITORING BLOCK (24 OD3 OD8 IOD8 Table 3.2 Buffer Type Descriptions DESCRIPTION 12 DATASHEET Datasheet BUFFER REQUIREMENT PER FUNCTION POWER (Note 3.1) WELL NOTES I VCC M I VCC M I /OD3 VCC M I VCC M OD8/O8 VCC OD8/OD8 VCC OD8/I VCC SMSC EMC6D103 ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet 3.3 3.3V Operation, 5V Tolerance The EMC6D103 is intended to operate with a nominal 3.3V power supply. The analog voltage pins are connected to voltage sources at their respective nominal levels. All digital signal pins are 3V switching, but are tolerant to 5V. SMSC EMC6D103 ...
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... External Diode Sensor Accuracy Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features MIN TYP MAX -3 ±0. ±0. DATASHEET Datasheet + +150 C UNITS COMMENTS <= T < <= T < Resolution -40 C <= T <= 125 <= T <= 100 Resolution C SMSC EMC6D103 ...
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... Supply Current CC Active Mode Sleep Mode Shutdown Mode Notes: Voltages are measured from the local ground potential, unless otherwise specified. Typical values are at TA=25°C and represent most likely parametric norm. SMSC EMC6D103 MIN TYP MAX ±2 TUE DNL ±1 PSS ± ...
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... The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb register. Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 16 DATASHEET Datasheet for conversion cycle timing for all SMSC EMC6D103 ...
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... Address Enable# pulled to ground through 10kΩ resistor Address Select pulled to VCC through a 10kΩ resistor In this way, there can three EMC6D103 devices on the SMBus at any time. Multiple EMC6D103 devices can be used to monitor additional processors and temperature zones. SMSC EMC6D103 Table 5.1 SMBus Slave Address Options ...
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... Figure 5.1 Address Selection on EMC6D103 5.2 Slave Bus Interface The EMC6D103 device SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports Write Byte and Read Byte protocols. ...
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... Undefined Registers Reads to undefined registers return 00h. Writes to undefined registers have no effect and return no error. 5.5 General Call Address Response The EMC6D103 will not respond to a general call address of 0000_000. SMSC EMC6D103 Table 5.2 SMBus Write Byte Protocol WR ACK REG. ADDR ...
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... The EMC6D103 device, which pulled SMBALERT# low, will acknowledge the Alert Response Address and respond with its device address. The 7-bit device address provided by the EMC6D103 device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one. ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet Note: The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC6D103 device will respond to the SMBus Alert Response address even if the INT# signal is not selected as ...
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... Input Monitoring The EMC6D103 device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the analog inputs and temperature sensors are stored in Reading Registers. The values in the reading registers can be accessed via the SMBus interface ...
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... The hardware monitor conversion clock is 45KHz ± 10%. Note 6.1 Note 6.2 Temperature conversions take 96 clocks, each (2.133ms nom.); Voltage conversions take 68 clocks, each (1.511ms nom). SMSC EMC6D103 Table 6.1 AVG[2:0] Bit Decoder MEASUREMENTS PER READING REMOTE INTERNAL DIODE 2 DIODE ...
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... Table 6.3 ADC Conversion Sequence REGISTER 1 Remote Diode Temp Reading 1 2 Ambient Temperature reading 3 VCC reading 4 +12V reading 5 +5V reading 6 +2.5V reading 7 Vccp (processor) reading 8 Remote Diode Temp Reading 2 23). Each measured value is compared to values stored 34. 24 DATASHEET Datasheet Auto SMSC EMC6D103 ...
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... Each interrupt status bit has a corresponding bit located in an interrupt enable register, which may be used to enable/disable the individual event from setting the status bit. See the following figure for the status and enable bits used to control the interrupt bits and INT# pin. SMSC EMC6D103 34. and on page 62 ...
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... Diode Fault on page 6.4.1 Diode Fault The EMC6D103 Chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the Remote Diode pins: The positive and negative terminal are an open circuit. Positive terminal is connected to VCC Positive terminal is connected to ground ...
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... This pin will remain low while the associated voltage error bit in the Interrupt Status Register 1 or Interrupt Status Register 2 is set. SMSC EMC6D103 Register 7Ch: Special Function Register on page 26. The following description assumes that the interrupt enable bits for all ...
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... Since any of these inputs can be Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Table 6.4 Low Power Mode Control Bits LPMD DESCRIPTION 0 Sleep Mode 1 Shutdown Mode x Monitoring 28 DATASHEET Datasheet 20. SMSC EMC6D103 ...
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... Remote Diode 1 (D1) or Remote Diode 2 (D2) status bits will be set in the Interrupt Status Register 1. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Fan Control Operating Mode on page SMSC EMC6D103 89. Table 6.5 Min/Max ADC Conversion Table + ...
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... READING (HEX) -127 81h -50 CEh -25 E7h -1 FFh 0 00h 1 01h 25 19h 50 32h 127 7Fh 128 80h 30 DATASHEET Datasheet 0 C. DIGITAL OUTPUT 1000 0001 1100 1110 1110 0111 1111 1111 0000 0000 0000 0001 0001 1001 0011 0010 0111 1111 1000 0000 SMSC EMC6D103 ...
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... Thermal Zones Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control mode. These zone assignments are as follows: Zone 1 = Remote Diode 1 (Processor) Zone 2 = Ambient (Internal) Temperature Sensor Zone 3 = Remote Diode 2 SMSC EMC6D103 31 DATASHEET Revision 0.3 (03-01-07) ...
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... Regardless of all changes made by the BIOS to the limit and parameter registers during configuration, the EMC6D103 will continue to operate based on default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the EMC6D103 will operate according to the values that were set by BIOS in the limit and parameter registers ...
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... PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. The EMC6D103 offers the option of generating an interrupt indicated by the INT# signal located on the PWM2 and TACH3 pins. ...
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... Auto Fan Control Operating Mode The EMC6D103 implements automatic fan control. In Auto Fan Mode, this device automatically adjusts the PWM duty cycle of the PWM outputs, according to the flow chart on the following page (see Figure 7.1 Automatic Fan Control Flow Diagramon page PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see 6.10, " ...
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... Zone x Low Temp Limit registers. This value will prevent the fan from oscillating between on and off if the temperature is around the minimum temperature limit. This value is programmed in Registers 6Dh-6Eh: Zone Hysteresis registers. SMSC EMC6D103 Auto Fan Mode Initiated ...
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... Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features shows the control for the auto fan algorithm. The part allows a minimum 36 DATASHEET Datasheet SMSC EMC6D103 ...
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... Note that more than one tachometer may be associated with a PWM, in which case all tachometers associated with a PWM must be in the valid range for spin-up to end. SMSC EMC6D103 MIN/OFF bit = 1 (Fan stays on when temperature is below minimum) ...
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... Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features duty cycle = 100% tach reading > tach reading < tach limit tach limit Spin Up Time Programmed Spin Up Time Figure 7.3 Spin Up Reduction Enabled 38 DATASHEET Datasheet SMSC EMC6D103 ...
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... SMSC EMC6D103 70). The actual duty cycle output is changed once per the period of the 40.) Table 6.2, “Conversion Cycle Timing,” on Table 7.1 PWM Ramp Rate PWM RAMP TIME (SEC) PWM STEP (TIME FROM 0% DUTY CYCLE TO 100% DUTY ...
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... DATASHEET Datasheet TIME PER PWM STEP PWM RAMP (PWM STEP SIZE = RATE 1/255) (HZ) 26 msec 38.46 18 msec 55.56 10 msec 100 5 msec 200 73h 74h 73h 73h 74h 73h 74h 74h 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 73h 74h 74h SMSC EMC6D103 ...
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... Tach Reading register will be set to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has occurred SMSC EMC6D103 In this mode, the fan tachometer simply counts the number of 90kHz ...
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... For the discussion below, an edge is a high-to-low or low-to-high transition (edges are numbered – refer to Figure 7.5, "PWM and Tachometer Concept"). Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 47.) 44) 42 DATASHEET Datasheet Linking Fan Summary of Operation for SMSC EMC6D103 ...
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... The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). SMSC EMC6D103 PWM “ON” ...
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... Note: The Slow Interrupt feature (SLOW) is configured in the TACHx Options registers at offsets 90h to 93h. The programmed number of edges occurs: Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 44 DATASHEET Datasheet SMSC EMC6D103 ...
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... Examples of Minimum RPMs Supported The following tables show minimum RPMs that can be supported with the different parameters. The first table uses 3 edges and the second table uses 2 edges. SMSC EMC6D103 below Table 7.2 for the one exception to this behavior. MAXIMUM TACHOMETER COUNT AT END OF PERIOD ...
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... TachPulse (Note 7.6) (30/T ) TachPulse 50% 100% 2673 1331 1777 887 1331 665 1063 532 884 442 660 330 439 220 331 166 = TachPulse SMSC EMC6D103 ...
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... TACH input is operating within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is ‘ON’. SMSC EMC6D103 MINIMUM RPM AT STRETCHED PULSE WIDTH 100MSE 200MSE ...
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... Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’. See the description of the PWM_TACH register. The default configuration is: PWM1 -> TACH1. PWM2 -> TACH2. PWM3 -> TACH3 & TACH4. Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 48 DATASHEET Datasheet SMSC EMC6D103 ...
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... Definition for the Lock and Start columns: Yes = Register is made read-only when the related bit is set Register is not made read-only when the related bit is set. Reg Read Reg Name Addr /Write 10h R/W SMSC Test Register 1Dh R/W Offset Register Ambient 1Eh R/W Offset Register 2 1Fh R/W ...
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Reg Read Reg Name Addr /Write 3Eh R Company ID 3Fh R Version / Stepping 40h R/W Ready/Lock/Start Note 8.2 41h R-C Interrupt Status Register 1 Note 8.3 42h R-C Interrupt Status Register 2 Note 8.3 43h R VID0-4 44h ...
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... SMSC Test Register 75h R SMSC Test Register 76h R/W SMSC Test Register 77h R SMSC Test Register 78h R/W SMSC Test Register 79h R/W SMSC Test Register 7Ah R SMSC Test Register 7Bh R/W SMSC Test Register Table 8.1 Register Summary (continued) Bit 7 ...
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... A/D Converter LSbs Reg 1 86h R A/D Converter LSbs Reg 2 87h R A/D Converter LSbs Reg 3 88h R A/D Converter LSbs Reg 4 89h R SMSC Test Register 8Ah R SMSC Test Register 8Bh R/W SMSC Test Register 8Ch R SMSC Test Register 8Dh R/W SMSC Test Register ...
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... PWM2 Option 96h R/W PWM3 Option 97h R/W SMSC Test Register 98h R/W SMSC Test Register 99-FEh R Reserved FFh R SMSC Test Register Table 8.1 Register Summary (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 MSb STCH2 STCH1 STCH0 3EDG MODE STCH2 STCH1 STCH0 ...
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... SMSC Test Register Bit 7 Bit 6 Bit 5 Bit 4 (MSb) TST7 TST6 TST5 TST4 Bit 7 Bit 6 Bit 5 (MSb DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) Value SMSC EMC6D103 00h 00h 00h 00h ...
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... C0h VCC 3.3V C0h +5V 5.0V C0h +12V 12.0V C0h The Voltage Reading registers will be updated automatically by the EMC6D103 Chip with a minimum frequency of 4Hz. These registers are read only – a write to these registers has no effect. SMSC EMC6D103 Bit 7 Bit 6 Bit 5 (MSb ...
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... Reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functioning properly (this corresponds to the diode fault interrupt status bits). The Temperature Reading registers will be updated automatically by the EMC6D103 Chip with a minimum frequency of 4Hz. ...
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... Note 8.8 These registers are only writable when the associated fan is in manual mode. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. SMSC EMC6D103 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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... Typically, the delay will be 1/(2*PWM frequency) seconds. Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features VALUE (DECIMAL 128 255 58 DATASHEET Datasheet VALUE (HEX) 00h 40h 80h FFh SMSC EMC6D103 ...
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... The four least significant bits of the Version / Stepping register [3:0] contain the current stepping of the EMC6D103 silicon. Stepping numbers are to begin from a value of 08h, to indicate that the register set is enhanced from previous hardware monitoring standards. The four most significant bits [7:4] reflect the version number, which will be fixed at 0110b ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Table 8.14 Ready/Lock/Start Monitoring DESCRIPTION When software writes this bit, the EMC6D103 enables monitoring and PWM output control functions based on the limit and parameter registers. Before this bit is set, the part does not update register values ...
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... Note below). The contents of this register are cleared (set to 0) automatically by the EMC6D103 after it is read by software, if the voltage or temperature no longer violates the limits set in the limit and parameter registers. Once set, the Interrupt Status Register 1 bits remain set until a read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no longer violate the limits set in the limit and parameter registers ...
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... Note below). The contents of this register are cleared (set to 0) automatically by the EMC6D103 after it is read by software, if the voltage no longer violate the limits set in the limit and parameter registers, if the temperature sensor error no loner exists the tach reading register is no longer above the minimum ...
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... Register Name Address Write 43h R VID0-4 The VID register contains the values of EMC6D103 VID0-VID4 input pins. This register indicates the status of the VID lines that interconnect the processor to the Voltage Regulator Module (VRM). SMSC EMC6D103 Table 8.18 Interrupt Status Register 2 DESCRIPTION 0 ...
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... EMC6D103 in the interrupt status registers (41-42h). Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as shown in Table 8 ...
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... EMC6D103 in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the Remote1- and Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[ the Interrupt Status Register 1 will be set. The temperature limits in these registers are represented as 8 bit, 2’ ...
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... Datasheet Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) Value Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value RES SPIN2 SPIN1 SPIN0 RES SPIN2 SPIN1 SPIN0 RES SPIN2 SPIN1 SPIN0 SMSC EMC6D103 FFh FFh FFh FFh FFh FFh FFh FFh 62h 62h 62h ...
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... Note that the Tachx minimum registers must be programmed to a value less than FFFFh in order for the spin-up reduction to work properly. SMSC EMC6D103 Table 8.26 Fan Zone Setting PWM CONFIGURATION Fan on zone 1 auto ...
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... Temperature LIMIT: PWM output at MIN FAN SPEED 68 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value FRQ3 FRQ2 FRQ1 FRQ0 C3h FRQ3 FRQ2 FRQ1 FRQ0 C3h FRQ3 FRQ2 FRQ1 FRQ0 C3h this range LIMIT+ RANGE: PWM Output at 100% Duty SMSC EMC6D103 ...
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... The PWM frequency bits [3:0] determine the PWM frequency for the fan. PWM Frequency Selection (Default =0011=29.3Hz) Table 8.29 Register Setting vs. PWM Frequency FREQ[3:0] 1000 - 1001 1011 - 1111 Range Selection (Default =1100=32 ° C) Table 8.30 Register Setting vs. Temperature Range RAN[3:0] SMSC EMC6D103 PWM FREQUENCY 0000 11.0 Hz 0001 14.6 Hz 0010 21.9 Hz 0011 29 ...
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... OFF3 OFF2 OFF1 RES RR2E RR2-2 RR2-1 RR2-0 PWM ACTION duty below LIMIT 1 At Min PWM Duty below LIMIT 70 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value RR1E RR1-2 RR1-1 RR1-0 00h RR3E RR3-2 RR3-1 RR3-0 00h SMSC EMC6D103 ...
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... These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode. SMSC EMC6D103 Table 8.33. For a description of the Ramp Rate Control logic see 38 ...
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... Table 8.35 PWM Duty vs. Register Setting VALUE (DECIMAL 128 . . . 255 Bit 7 Bit 6 Bit 5 (MSb LIMIT (DEC) -127 . . . - DATASHEET Datasheet VALUE (HEX) 00h . . . 40h . . . 80h . . . FFh Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb LIMIT (HEX) 81h . . . CEh . . . 00h . . . SMSC EMC6D103 Value 5Ah 5Ah 5Ah ...
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... Table 8.39 Absolute Limit vs. Register Setting ABSOLUTE LIMIT -127 ° -50 ° ° SMSC EMC6D103 LIMIT (DEC) LIMIT (HEX) 50 32h . . . . . . 127 7Fh Bit 7 Bit 6 Bit 5 ...
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... RES RES 74 DATASHEET Datasheet 32h . . . 7Fh Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) Value H1-0 H2- H2-2 H2-1 H2-0 3 H3-0 RES RES RES RES Bit 0 Default Bit 4 Bit 3 Bit 2 Bit 1 (LSb) RES RES RES RES XEN SMSC EMC6D103 44h 40h Value 00h ...
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... R/W SMSC Test Register This is a read/write register. Writing this register may produce unwanted results. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. SMSC EMC6D103 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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... Table 8.47 AVG[2:0] Bit Decoder AVERAGES PER READING REM DIODE 2 INTERNAL DIODE 128 128 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) SMSC INTEN MONMD LPMD (Table 8.47, "AVG[2:0] Bit ALL VOLTAGE READINGS (+2.5V, +5V, +12V, VCCP, AND VCC SMSC EMC6D103 Value 40h ...
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... Bit[4] Reserved Bit[5] 5V Error Enable Bit[6] 12V Error Enable Bit[7] VCC Error Enable The individual voltage error event bits are defined as follows: 0=disable 1=enable. See Figure 6.1 Interrupt Controlon page SMSC EMC6D103 AVERAGES PER READING REM DIODE 2 INTERNAL DIODE Bit 7 Bit 6 ...
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... INIT SMSC SMSC SUREN Bit 7 Bit 6 Bit 5 Bit 4 (MSb) RES RES RES TACH4 78 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TRDY RES P2INT T3INT 10h Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TACH3 TACH2 TACH1 TACH 1Eh SMSC EMC6D103 ...
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... Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below. SMSC EMC6D103 26. Bit 7 ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Table 8.52 Bit Combinations PWM Associated With Tachx Bit 7 Bit 6 Bit 5 Bit 4 (MSb) RES RES RES RES 26. 80 DATASHEET Datasheet PWM1 PWM2 PWM3 Reserved Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value D2EN D1EN AMB TEMP 0Eh SMSC EMC6D103 ...
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... R/W SMSC Test Register This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register must not be written. Writing this register may produce unexpected results. SMSC EMC6D103 Bit 7 Bit 6 Bit 5 Bit 4 ...
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... Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 N/A Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value MODE EDG1 EDG0 SLOW CCh MODE EDG1 EDG0 SLOW CCh MODE EDG1 EDG0 SLOW CCh MODE EDG1 EDG0 SLOW CCh SMSC EMC6D103 ...
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... PWM3 Option These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only) 00=once a second (default) SMSC EMC6D103 Bit 7 Bit 6 Bit 5 Bit 4 ...
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... TST7 TST6 TST5 TST4 Bit 7 Bit 6 Bit 5 Bit 4 (MSb) TST7 TST6 TST5 TST4 84 DATASHEET Datasheet Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 5Ah Bit 0 Default Bit 3 Bit 2 Bit 1 (LSb) Value TST3 TST2 TST1 TST0 F1h SMSC EMC6D103 ...
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... Register FFh: SMSC Test Register Table 8.65 Register FFh: SMSC Test Register Register Read Register Address /Write Name 98h R SMSC Test Register This register is an SMSC Test register. SMSC EMC6D103 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSb) TST7 TST6 TST5 TST4 TST3 ...
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... Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features t1 t2 Figure 9.1 PWMx Output Timing Table 9.1 Timing for PWM[1:3] Outputs MIN 0.04 9. During Spin-up the PWM High Time can reach a 100% or Full On. PWM 86 DATASHEET Datasheet TYP MAX UNITS 90.9 msec 99 PWM SMSC EMC6D103 ...
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... I version 2.0, Dec. 1998. Note 9.4 At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. Note 9.5 If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (T SMSC EMC6D103 SU;STA t ...
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... DATASHEET Datasheet REMARKS Overall Package Height Standoff Body Thickness X Body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Pitch Lead Foot Angle Lead Width Coplanarity SMSC EMC6D103 ...
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... SMSC EMC6D103 V 2 CCPIN <0.0172 <0.013 <0.012 0.017–0.034 0.013–0.026 0.012–0.023 0.034–0.052 0.026– ...
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... PWMx 2.2k Figure B.1 Fan Drive Circuitry (Apply to PWM Driving Two Fans) Revision 0.3 (03-01-07) Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features 3.3V MMBT3904 90 DATASHEET Datasheet 12V M MMBT2222 Fan1 M MMBT2222 Fan2 SMSC EMC6D103 ...
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... Fan Note: For fans controlled directly by a PWM suggested to implement the optional diode (D1) to protect the tachometer input from large voltage spikes generated by the fan. Figure B.3 Fan Tachometer Circuitry (Apply to Each Fan) SMSC EMC6D103 3.3V 470 MMBT2222 3.3V Tach ...
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... Figure B.4 Remote Diode (Apply to Remote2 Lines) Notes: 1. 2.2nF cap is optional and should be placed close to the EMC6D103 if used. 2. The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable. 3. The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded guard tracks on each side ...