EMC6D103-CZC SMSC, EMC6D103-CZC Datasheet - Page 78

• Manufacturer Part Number: EMC6D103-CZC
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC6D103-CZC

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision 0.3 (03-01-07)
8.2.29
8.2.30
Register
Address
Register
Address
80h
7Fh
Read/
Write
R/W
Read/
Write
R/W
Register 7Fh: Configuration Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register contains the following bits:
Bit[0] TACH3/INT# pin select: 0=TACH, 1=INT#
Bit[1] PWM2/INT# pin select: 0=PWM, 1=INT#
Bit[2] Reserved
Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers
have valid values. This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid.
Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on
feedback from all fan tachometers associated with each PWM. 0=disable, 1=enable (default)
Bit[5] SMSC Reserved
This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause
unwanted results.
Bit[6] SMSC Reserved
This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause
unwanted results.
Bit[7] Initialization
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers
except the Reading Registers to their default values.
Register 80h: Interrupt Enable 2 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),
which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] TACH (Group TACH Enable)
Interrupt Enable 2 (Fan
Register Name
Register Name
Configuration
Tachs)
Table 8.50 Register 80h: Interrupt Enable 2 Register
Table 8.49 Register 7Fh: Configuration Register
Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
(MSb)
(MSb)
Bit 7
RES
Bit 7
INIT
DATASHEET
Bit 6
RES
SMSC
Bit 6
78
Bit 5
RES
SMSC
Bit 5
TACH4
Bit 4
SUREN
Bit 4
TACH3
Bit 3
TRDY
Bit 3
TACH2
Bit 2
Bit 2
RES
TACH1
P2INT
Bit 1
Bit 1
SMSC EMC6D103
T3INT
(LSb)
TACH
(LSb)
Bit 0
Bit 0
Datasheet
Default
Default
Value
Value
10h
1Eh