AD1837AAS-REEL Analog Devices Inc, AD1837AAS-REEL Datasheet - Page 22

• Manufacturer Part Number: AD1837AAS-REEL
• Description: IC CODEC 2ADC/8DAC 24 BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1837AAS-REEL

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 5.5V
• Package Type: MQFP
• For Use With: EVAL-AD1837AEB - BOARD EVALUATION FOR AD1837A
• Lead Free Status / Rohs Status: Not Compliant

AD1837A
CASCADE MODE
Dual AD1837A Cascade
The AD1837A can be cascaded to an additional AD1837A,
which, in addition to six external stereo ADCs, can be used to
create a 32-channel audio system with 16 inputs and 16 outputs.
The cascade is designed to connect to a SHARC DSP and operates
in a time division multiplexing (TDM) format. Figure 14 shows
the connection diagram for cascade operation. The digital inter-
face for both parts must be set to operate in Auxiliary 512 mode
by programming ADC Control Register 2. AD1837A No. 1 is
set as a master device by connecting the M/S pin to DGND and
AD1837A No.2 is set as a slave device by connecting the M/S to
ODVDD. Both devices should be run from the same MCLK
and PD/RST signals to ensure that they are synchronized.
(SLAVE)
SHARC
ABCLK
TFSx/
DTx
DRx
RFSx
RCLKx
TCLKx
DTx
DRx
RFSx
TFSx
DRx
DTx
L1
L1
AUX ADC
(SLAVE)
L2
MSB
L2
MSB
ASDATA
ALRCLK
ABCLK
AD1837A NO. 1 DACs
AD1837A NO. 1 ADCs
L3
L3
MSB – 1
MSB – 1
256 ABCLKs
Figure 15. AD1837A Cascade Timing
L4
L4
AUX ADC
(SLAVE)
Figure 14. AD1837A Cascade
R1
R1
32 ABCLKs
R2
R2
AD1837A NO. 1
LSB
LSB
(MASTER)
AUX ADC
(SLAVE)
R3
R3
DSDATA
–22–
R4
R4
DON’T CARE
With Device 1 set as a master, it will generate the frame-sync
and bit clock signals. These signals are sent to the SHARC and
Device 2 ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and also clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending
DAC data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers will have
been clocked into the SHARC and been replaced by DAC data,
which is subsequently written to the DACs. Figure 15 shows the
timing diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
AD1837A NO. 2 DACs
AD1837A NO. 2 ADCs
L3
L3
256 ABCLKs
ASDATA
ALRCLK
ABCLK
L4
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1837A NO. 2
(SLAVE)
AUX ADC
R4
(SLAVE)
R4
DSDATA
REV. A