CY7C63801-PXC Cypress Semiconductor Corp, CY7C63801-PXC Datasheet - Page 57

• Manufacturer Part Number: CY7C63801-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63801-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

18. Regulator Output
18.1 VREG Control
Table 18-1. VREG Control Register (VREGCR) [0x73] [R/W]
Document 38-08035 Rev. *N
Bit [7:2]: Reserved
Bit 1: Keep Alive
Keep Alive, when set, allows the voltage regulator to source up to 20 µA of current when the voltage regulator is disabled.
P12CR[0],P12CR[7] must be cleared.
0 = Disabled
1 = Enabled
Bit 0: VREG Enable
This bit turns on the 3.3 V voltage regulator. The voltage regulator only functions within specifications when V
This block must not be enabled when V
0 = Disable the 3.3 V voltage regulator output on the VREG/P1.2 pin.
1 = Enable the 3.3 V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled.
Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide
the alternate voltage.
Read/Write
Default
Field
Bit #
7
–
0
6
–
0
CC
is below 4.35V—although no damage or irregularities occur if it is enabled below 4.35 V.
5
–
0
Reserved
4
–
0
3
–
0
CY7C63310, CY7C638xx
2
–
0
Keep Alive
R/W
1
0
CC
is above 4.35 V.
VREG Enable
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R/W
0
0
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