LAN9211-ABZJ SMSC, LAN9211-ABZJ Datasheet - Page 18

• Manufacturer Part Number: LAN9211-ABZJ
• Description: IC ETHERNET CTLR SGL CHIP 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9211-ABZJ

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Supply Current (max): 86 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 86mA
• Supply Voltage Range: 2.97V To 3.63V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1049-6

Revision 2.7 (03-15-10)
Activity Indicator),
Common Ground
General Purpose
+3.3V I/O Power
nLED1 (Speed
nLED2 (Link &
nLED3 (Full-
+3.3V Analog
+1.8V Analog
Core Voltage
Decoupling
Indicator
Indicator),
I/O data,
Duplex
NAME
Power
Power
Note 2.1
).
VDD_CORE
Please refer to the SMSC application note AN16.6 - “Migrating from LAN9215 to the
LAN9210/LAN9211” for additional details.
GPIO[2:0]/
nLED[3:1]
VDD_A33
VDD_A18
SYMBOL
VDD_IO
VSS
Table 2.4 System and Power Signals (continued)
BUFFER
IS/O12/
TYPE
OD12
P
P
P
P
P
DATASHEET
High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
18
1 pad
PINS
NUM
3
5
3
1
2
Common Ground
+1.8V analog power supply pin. This pin must
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain.
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100Mbs,
during auto-negotiation and when the cable is
disconnected. This signal is driven high only
during 10Mbs operation.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the LAN9211
detects a valid link. This signal is pulsed high
(LED off) for 80mS whenever transmit or
receive activity is detected. This signal is then
driven low again for a minimum of 80mS, after
which time it will repeat the process if TX or RX
activity is detected. Effectively, LED2 is
activated solid for a link. When transmit or
receive activity is sensed LED2 will flash as an
activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in full-
duplex mode.
+3.3V I/O logic power supply pins
+3.3V analog power supply pins. See
be connected externally to VDD_CORE. See
Note
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01uF decoupling capacitor. In
addition, pin 2 requires a bulk 4.7uF capacitor
(<2 Ohm ESR) in parallel. These pins must not
be used to supply power to other external
devices. See
2.1.
Note
DESCRIPTION
2.1.
SMSC LAN9211
Note
Datasheet
2.1.