LAN9118-MT SMSC, LAN9118-MT Datasheet - Page 39

• Manufacturer Part Number: LAN9118-MT
• Description: IC ETHERNET CTRLR 10/100 100TQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHYr

Specifications of LAN9118-MT

• Controller Type: Ethernet Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 100BASE-TX or 10BASE-T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1013

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
3.10.2.2
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.8
Once the READY bit is set, the LAN9118 is ready to resume normal operation. At this time the WUPS
field can be cleared.
D2 Sleep
In this state, as shown in
placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY
(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The
PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,
the LAN9118 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the
D2 state.
Note 3.9
If properly enabled via the ED_EN and PME_EN bits, LAN9118 will assert the PME hardware signal
upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b.
Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return LAN9118
to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required
to check the READY bit and verify that it is set before attempting any other reads or writes of the
device. Before LAN9118 is fully awake from this state the EDPWRDOWN bit in register 17 of the PHY
must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit until the
READY bit is set. After clearing the EDPWRDOWN bit the LAN9118 is ready to resume normal
operation. At this time the WUPS field can be cleared.
The host must do only read accesses prior to the ready bit being set.
If carrier is present when this state is entered detection will occur immediately.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.9 Power Management States
D0
Table
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
3.9, all clocks to the MAC and host bus are disabled, and the PHY is
DATASHEET
39
RX Power Mgmt. Block
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
Revision 1.5 (07-11-08)
OFF
OFF
OFF
D2