DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 165

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS31256 256-Channel, High-Throughput HDLC Controller
Test-Logic-Reset. The TAP controller is in the Test-Logic-Reset state upon DS31256 power-up. The
instruction register contains the IDCODE instruction. All system logic on the DS31256 operates
normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction
and test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK
moves the controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the
controller to the Select-IR-Scan state.
Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If
the instruction does not call for a parallel load or the selected register does not allow parallel loads, the
test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR
state if JTMS is low or it goes to the Exit1-DR state if JTMS is high.
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO
and shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-
DR state, which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the
controller in the Pause-DR state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the
current instruction retain their previous states. The controller remains in this state while JTMS is low. A
rising edge on JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-
DR state and terminates the scanning process. A rising edge on JTCLK with JTMS low enters the Shift-
DR state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift
register path of the test registers into the data output latches. This prevents changes at the parallel output
because of changes in the shift register. A rising edge on JTCLK with JTMS low puts the controller in the
Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test registers retain their previous states. The instruction register remains
unchanged during this state. With JTMS low, a rising edge on JTCLK moves the controller into the
Capture-IR state and initiates a scan sequence for the instruction register. JTMS high during a rising edge
on JTCLK puts the controller back into the Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed
value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK,
the controller enters the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters
the Shift-IR state.
Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO
and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register as
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