DS31256 Maxim Integrated Products, DS31256 Datasheet - Page 35

• Manufacturer Part Number: DS31256
• Description: IC CTRLR HDLC 256-CHANNEL 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS31256

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS31256 256-Channel, High-Throughput HDLC Controller
interrupt enable for the receive COFA (IERC) and interrupt enable for the transmit COFA (IETC)
control bits in the RP[n]CR and TP[n]CR registers, respectively.
The BERT receiver reports three events: a change in the receive synchronizer status, a bit error being
detected, and if either the bit counter or the error counter overflows. Each of these events can be masked
within the BERT function through the BERT control register (BERTC0). If the software detects that the
BERT has reported an event, the software must read the BERT status register (BERTEC0) to determine
which event(s) has occurred.
The SM register also reports events as they occur in the PCI bus and the local bus. There are no control
bits to stop these events from being reported in the SM register. When the local bus is operated in the
PCI bridge mode, SM reports any interrupts detected through the local bus LINT input signal pin and if
any timing errors occur because the external timing signal LRDY. When the local bus is operated in the
configuration mode, the LBINT and LBE bits are meaningless and should be ignored.
SV54 Register
The status for receive V.54 detector (SV54) register reports if the V.54 loopback detector has either
timed out in its search for the V.54 loop-up pattern or if the detector has found and verified the loop-
up/down pattern. There is a separate status bit (SLBP) for each port. When set, the host must read the
VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the
V.54 detector. When the V.54 detector experiences a timeout in its search for the loop-up code
(VTO = 1), then the SLBP status bit is continuously set until the V.54 detector is reset by the host,
toggling the VRST bit in RP[n]CR register. There are no control bits to stop these events from being
reported in the SV54 register. See
Figure 5-1
for details on the status bits and Section
6
for details on the
operation of the V.54 loopback detector.
SDMA Register
The status DMA (SDMA) register reports events pertaining to the receive and transmit DMA blocks as
well as the receive HDLC controller and FIFO. The SDMA reports when the DMA reads from either the
receive free queue or transmit pending queue or writes to the receive or transmit done queues. Also
reported are error conditions that might occur in the access of one of these queues. The SDMA reports if
any of the HDLC channels experiences an FIFO overflow/underflow condition and if the receive HDLC
controller encounters a CRC error, abort signal, or octet length problem on any of the HDLC channels.
The host can determine which specific HDLC channel incurred an FIFO overflow/underflow, CRC error,
octet length error, or abort by reading the status bits as reported in done queues, which are created by the
DMA. There are no control bits to stop these events from being reported in the SDMA register.
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