PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 29

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

7.2.4
Table 7-6.
Notes:
2137D–HIREL–08/05
Num
12b1
12b2
12a
12b
12c
12d
12e
13a
13b
14a
14b
1. All memory and related interface output signal specifications are specified from the V
2. All PCI signals are measured from OV
3. All output timings assume a purely resistive 50Ω load (See
4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TRDY, FRAME, STOP, DEVSEL,
5. PCI hold times can be varied, see
6. These specifications are for the default driver strengths indicated in
Characteristics
PCI_SYNC_IN to Output Valid, 66 MHz PCI, with SDMA4 pulled-
down to logic 0 state. See
PCI_SYNC_IN to Output Valid, 33 MHz PCI, with SDMA4 in the
default logic 1 state. See
Memory Interface Signals, SDRAM_SYNC_IN to Output Valid
Memory Interface Signal: CKE (100 MHz Device),
SDRAM_SYNC_IN to Output Valid
Memory Interface Signal: CKE (66 MHz Device),
SDRAM_SYNC_IN to Output Valid
Epic, Misc. Debug Signals, SDRAM_SYNC_IN to Output Valid
Two-wire interface, SDRAM_SYNC_IN to Output Valid
60x Processor Interface Signals, SDRAM_SYNC_IN to Output Valid
Output Hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled-down to
logic 0 states. See
Output Hold, 33 MHz PCI, with SDMA4 in the default logic 1 state
and SDMA3 pulled-down to logic 0 state. See
Output Hold (For All Others)
PCI_SYNC_IN to Output High Impedance (T
SDRAM_SYNC_IN to Output High Impedance (For All Others)
Output AC Timing Specification
ory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See
question for 3.3V PCI signaling levels. See
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA.
hold times. The values shown for item 13a are for PCI compliance.
Output AC Timing Specifications
(3)(6)
Table 7-6
on page 28
At recommended operating conditions (see
Figure 7-8.
Table
Figure
7-7.
Figure
provides the processor bus AC timing specifications for the PC107A. See
and
7-9.
7-9.
OUTPUT
AC Test Load for the PC107A
”PCI Signal Output Hold Timing” on page 30
Figure 7-6 on page
PIN
DD
/2 of the rising edge of PCI_SYNC_IN to 0.285*OV
off
Figure 7-6 on page
Table
for PCI)
7-7.
Figure 7-5 on page
Z0 = 50Ω
28.
Output measurements are made at the device pin.
Figure 7-8 on page
28.
Table 5-2 on page
Table 7-2 on page
28.
Min
1.0
2.0
–
–
–
–
–
–
–
–
1
–
–
29). Output timings are measured at the pin;
for information on programmable PCI output
M
RL = 50Ω
= 1.4V of the rising edge of the mem-
12) with
22.
DD
Max
11.0
14.0
6.0
5.5
5.5
6.0
5.0
5.5
4.0
9.0
–
–
or 0.615*OV
LV
DD
OVdd/2
= 3.3
Unit
DD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PC107A
±
of the signal in
0.3V
Figure 7-5
Notes
(2)(4)(5)
(2)(4)(5)
(2)(4)
(2)(4)
(2)(4)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
29