PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 4

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

4
PC107A
• Two-channel Integrated DMA Controller (Writes to ROM/Port × Not Supported)
• Message Unit
• Two-wire Interface Controller with Full Master/Slave Support (Except Broadcast All)
• Embedded Programmable Interrupt Controller (EPIC)
• Integrated PCI Bus, CPU, and SDRAM Clock Generation
• Programmable PCI Bus, 60x, and Memory Interface Output Drivers
• Dynamic Power Management – Supports 60x Nap, Doze, and Sleep Modes
• Programmable Input and Output Signals with Watchpoint Capability
• Built-in PCI Bus Performance Monitor Facility
• Debug Features
• Processor Interface
– PCI agent mode capability
– Address translation unit
– Some internal configuration registers accessible from PCI
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering-read or write discontinuous memory
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– PCI-to-local memory
– PCI memory-to-local memory
– Two doorbell registers
– An extended doorbell register mechanism that facilitates interprocessor
– Two inbound and two outbound messaging registers
– I
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers
– Error injection/capture on data path
– IEEE 1149.1 (JTAG)/test interface
– Supports up to two PowerPC
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64/32-bit data bus supported at 100 MHz
– Supports full memory coherency
– Supports optional local bus slave
– Decoupled address and data buses for pipelining of 60x accesses
– Store gathering on 60x-to-PCI writes
– Concurrent transactions on 60x and PCI buses supported
communication through interrupts in a dual-local-processor system
2
O message controller
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microprocessors with 60x bus interface
2137D–HIREL–08/05