DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 64

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TRANSMIT A HDLC MESSAGE
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
2. Enable either the THALF or TNF interrupt
3. Read THIR to obtain TFULL status
4. Repeat step 3
5. Wait for interrupt, skip to step 3
6. Disable THALF or TNF interrupt and enable TMEND interrupt
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
18.
Each Framer/Formatter has the ability to extract/insert data from/ into the Facility Data Link (FDL) in the
ESF framing mode and from/into Fs–bit position in the D4 framing mode. Since SLC–96 utilizes the Fs–
bit position, this capability can also be used in SLC–96 applications. The DS21Q42 contains a complete
HDLC and BOC controller for the FDL and this operation is covered in Section 19.1. To allow for
backward compatibility between the DS21Q42 and earlier devices, the DS21Q42 maintains some legacy
functionality for the FDL and this is covered in Section 19.2. Section 19.3 covers D4 and SLC–96
operation. Please contact the factory for a copy of C language source code for implementing the FDL on
the DS21Q42.
19.1 HDLC AND BOC CONTROLLER FOR THE FDL
19.1.1 General Overview
The DS21Q42 contains a complete HDLC controller with 64–byte buffers in both the transmit and
receive directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC
controller performs all the necessary overhead for generating and receiving Performance Report
Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The
HDLC controller automatically generates and detects flags, generates and checks the CRC check sum,
generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the
HDLC data stream. The 64–byte buffers in the HDLC controller are large enough to allow a full PRM to
be received or transmitted without host intervention. The BOC controller will automatically detect
incoming BOC sequences and alert the host. When the BOC ceases, the DS21Q42 will also alert the
host. The user can set the device up to send any of the possible 6–bit BOC codes.
There are thirteen registers that the host will use to operate and control the operation of the HDLC and
BOC controllers. A brief description of the registers is shown in Table 19–1.
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register
A. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the
B. If TFULL=1, then skip to step 5
last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6)
FDL/Fs EXTRACTION AND INSERTION
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