DP8419N-70 National Semiconductor, DP8419N-70 Datasheet

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DP8419N-70

Manufacturer Part Number
DP8419N-70
Description
IC CTRLR 256K DRAM 48-DIP
Manufacturer
National Semiconductor
Datasheet

Specifications of DP8419N-70

Controller Type
Dynamic RAM (DRAM) Controller, Drivers
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
150mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
48-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP8419N-70
C 1995 National Semiconductor Corporation
DP8417 NS32817 8418 32818 8419 32819 8419X
32819X 64k 256k Dynamic RAM Controller Drivers
General Description
The DP8417 8418 8419 8419X represent a family of 256k
DRAM Controller Drivers which are designed to provide
‘‘No-Waitstate’’ CPU interface to Dynamic RAM arrays of up
to 2 Mbytes and larger Each device offers slight functional
variations of the DP8419 design which are tailored for differ-
ent system requirements All family members are fabricated
using National’s new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed level of integration and power
consumption
Each device integrates the following critical 256k DRAM
controller functions on a single monolithic device ultra pre-
cise delay line 9-bit refresh counter fall-through row col-
umn and bank select input latches Row Column address
muxing logic on-board high capacitive-load RAS CAS and
Write Enable
signal timing for all the above
There are four device options of the basic DP8419 Control-
ler The DP8417 is pin and function compatible with the
DP8419 except that its outputs are TRI-STATE
DP8418 changes one pin and is specifically designed to
offer an optimum interface to 32 bit microprocessors The
DP8419X is functionally identical to the DP8419 but is avail-
able in a 52-pin DIP package which is upward pin compati-
ble with National’s new DP8429D 1 Mbit DRAM Controller
Driver
Each device is available in plastic DIP Ceramic DIP and
Plastic Chip Carrier (PCC) packaging (Continued)
TRI-STATE is a registered trademark of National Semiconductor Corp
PAL is a registered trademark of and used under license with Monolithic Memories Inc
System Diagram
Address output drivers and precise control
TL F 8396
The
Operational Features
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Contents
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Makes DRAM Interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Eliminates 15 to 20 SSI MSI components for significant
board real estate reduction system power savings and
the elimination of chip-to-chip AC skewing
On-board ultra precise delay line
On-board high capacitive RAS CAS WE and address
drivers (specified driving 88 DRAMs directly)
AC specified for directly addressing up to 8 Megabytes
Low power high speed bipolar oxide isolated process
Upward pin and function compatible with new DP8428
DP8429 1 Mbit DRAM controller drivers
Downward pin and function compatible with DP8408A
DP8409A 64k 256k DRAM controller drivers
4 user selectable modes of operation for Access and
Refresh (2 automatic 2 external)
System and Device Block Diagrams
Recommended Companion Components
Device Connection Diagrams and Pin Definitions
Family Device Differences
(DP8419 vs DP8409A 8417 8418 8419X)
Mode of Operation
(Descriptions and Timing Diagrams)
Application Description and Diagrams
DC AC Electrical Specifications Timing Diagrams and
Test Conditions
PRELIMINARY
RRD-B30M105 Printed in U S A
August 1989
TL F 8396 – 25

Related parts for DP8419N-70

DP8419N-70 Summary of contents

Page 1

... National’s new DP8429D 1 Mbit DRAM Controller Driver Each device is available in plastic DIP Ceramic DIP and Plastic Chip Carrier (PCC) packaging (Continued) TRI-STATE is a registered trademark of National Semiconductor Corp PAL is a registered trademark of and used under license with Monolithic Memories Inc System Diagram C 1995 National Semiconductor Corporation ...

Page 2

General Description (Continued) In order to specify each device for ‘‘true’’ worst case operat- ing conditions all timing parameters are guaranteed while the chip is driving the capacitive load of 88 DRAMs includ- ing trace capacitance The chip’s delay timing ...

Page 3

Block Diagrams DP8417 8419 and 8419X DP8418 8396 – 8396 – 27 ...

Page 4

... Connection Diagrams (Dual-In-Line Package) Order Number DP8417D-70 DP8417D-80 DP8417N-70 DP8417N-80 DP8418D-70 DP8418D-80 DP8418N-70 DP8418N-80 DP8419D-70 DP8419D-80 DP8419N-70 DP8419N-80 See NS Package Number D48A D52A or N48A TL F 8396– 8396– 30 DP8419XD-70 or DP8419XD- 8396– 29 ...

Page 5

Connection Diagrams (Continued) Order Number DP8417V-70 DP8417V-80 DP8418V-70 DP8418V-80 DP8419V-70 or DP8419V-80 Plastic Chip Carrier Package Plastic Chip Carrier Package See NS Package Number V68A 8396 – 8396 – 32 ...

Page 6

Family Device Differences DP8417 vs DP8419 The DP8417 is identical to the DP8419 with the exception that its RAS CAS WE and Q (Multiplexed Address) outputs are TRI-STATE when CS (Chip Select) is high and the chip is not in ...

Page 7

Pin Definitions (Continued) indicating that no hidden refresh was performed while RFCK was high When this pin is set low by an external gate the on-chip refresh counter is reset to all zeroes WIN Write Enable Input WE Write Enable ...

Page 8

Mode Features Summary 4 modes of operation 2 access and 2 refresh Y Automatic or external control selected by the user Y Auto access mode provides RAS row to column Y change and then CAS automatically Choice between two different ...

Page 9

DP8419 Mode Descriptions DP8419 Interface Between System FIGURE 1a DP8419 with any 16k DRAMS Only LS 7 Bits of Refresh Counter used for the 7 Row Addresses MSB not used but can toggle FIGURE 1b DP8419 with 128 Row x ...

Page 10

DP8419 Mode Descriptions Indicates Dynamic RAM Parameters FIGURE 2a External Control Refresh Cycle (Mode 0) (Continued) FIGURE 2b Burst Refresh Mode 8396– 8396– 10 ...

Page 11

DP8419 Mode Descriptions MODE 1–AUTOMATIC FORCED REFRESH In Mode 1 the R C (RFCK) pin becomes RFCK (refresh cycle clock) and the CASIN (RGCK) pin becomes RGCK (RAS generator clock) If RFCK is high and Mode 1 is en- tered ...

Page 12

DP8419 Mode Descriptions The Refresh Request on RFI O is terminated as RAS goes low This signal may be used to end the refresh earlier than it normally would as described above pulled high while the RAS ...

Page 13

DP8419 Mode Descriptions FIGURE 5a Read Cycle Timing (Mode 4) FIGURE 5b Write Cycle Timing (Mode 4) (Continued 8396 – 8396 – 14 ...

Page 14

DP8419 Mode Descriptions Page or Nibble mode may be performed by toggling CASIN once the initial access has been completed In the case of page mode the column address must be changed before CASIN goes low to access a new ...

Page 15

DP8419 Mode Descriptions Indicates Dynamic RAM Parameters (Refer to Figure mode 5 the selected RAS follows RASIN immediately as in mode 4 to strobe the row address into the DRAMs The row address remains valid on the ...

Page 16

DP8419 Mode Descriptions Once it is started a hidden refresh will continue even if RFCK goes low However CS must be high throughout the refresh (until RASIN goes high) These hidden refreshes are valuable in that they do not delay ...

Page 17

DP8419 Mode Descriptions FIGURE 7b Typical Application of DP8419 Using Modes 5 and 1 FIGURE 7c Typical Application of DP8418 Using Modes 5 and 1 (Continued 8396 – 8396 – 33 ...

Page 18

... CSRL1 an easy interface to most popular microprocessors (Mo- torola 68000 family National Semiconductor 32032 fami- ly Intel 8086 family and the Zilog Z8000 family) 3) Less skew in memory timing parameters because all crit- ical components are on one chip (many discrete drivers ...

Page 19

Applications (Continued) FIGURE 8 Connecting the DP8419 Between the 16-bit Microprocessor and Memory T is microprocessor’s clock period FIGURE 9 DP8419 Auto Refresh Access with WAIT States 8396 – 8396 – 21 ...

Page 20

... FIGURE 11a Output Load Circuit TL F 8396– 22 FIGURE 11b DP8417 TRI-STATE Waveforms Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply voltage V CC Storage Temperature Range Input Voltage ...

Page 21

Electrical Characteristics V Symbol Parameter V Input Clamp Voltage C I Input High Current for all Inputs IH I RSI Output Load Current for RFI Input Low Current for all Inputs ADS R C ...

Page 22

Switching Characteristics DP8417 DP8418 DP8419 DP8419X 10 unless otherwise noted (Notes The output load capacitance is typical for 4 banks DRAMs ...

Page 23

Switching Characteristics DP8417 DP8418 DP8419 DP8419X 10 unless otherwise noted (Notes The output load capacitance is typical for 4 banks DRAMs ...

Page 24

Switching Characteristics DP8417 DP8418 DP8419 DP8419X 10 unless otherwise noted (Notes The output load capacitance is typical for 4 banks DRAMs ...

Page 25

Input Capacitance (Note Symbol Parameter C Input Capacitance ADS RASIN IN C Input Capacitance All Other Inputs IN Note 1 ‘‘Absolute Maximum Ratings’’ are the values beyond which the safety ...

Page 26

Physical Dimensions inches (millimeters) Order Number DP8417D-70 or DP8417D-80 DP8418D-70 or DP8418D-80 or DP8419D-70 or DP8419D-80 Order Number DP8419XD-80 or DP8419XD-70 Hermetic Dual-in-Line Package (D) NS Package Number D48A Hermetic Dual-in-Line Package (D) NS Package Number D52A 26 ...

Page 27

... Physical Dimensions inches (millimeters) (Continued) Order Number DP8417N-70 or DP8417N-80 or DP8418N-70 or DP8418N-80 or DP8419N-70 or DP8419N-80 Molded Dual-in-Line Package (N) NS Package Number N48A 27 ...

Page 28

... Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a Lit 103070 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...

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