DP83820BVUW National Semiconductor, DP83820BVUW Datasheet
DP83820BVUW
Specifications of DP83820BVUW
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DP83820BVUW Summary of contents
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... Mb/s physical layer devices — Ten-Bit Interface (TBI) for support of 1000BASE-X System Diagram PCI Bus © 2001 National Semiconductor Corporation — Virtual LAN (VLAN) and long frame support. VLAN tag insertion support for transmit packets. VLAN tag detection and removal for receive packets — ...
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Connection Diagram RXD0 157 RXD1 158 RXD2 159 RXD3 160 VSSIO 161 VDDIO 162 RXD4 163 RXD5 164 RXD6 165 RXD7 166 RXDV/RXD8 167 RXER/RXD9 168 CRS/SIG_DET 169 COL 170 RXEN 171 PHYRSTN 172 COREVSS 173 COREVDD 174 PMEN ...
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Pin Descriptions PCI Interface Symbol Pin No(s) Direction AD31-0 188, 189, 190, 191, 192, 193, 194, 195, 199, 200, 202, 203, 204, 207, 208, 1, 14, 15, 17, 18, 19, 21, 22, 23, 25, 26, 28, 29, 31, 32, ...
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Pin Descriptions (Continued) PCI Interface Symbol Pin No(s) Direction SERRN 11 STOPN 9 TRDYN 6 PMEN 175 3VAUX 86 PWRGOOD 85 CLKRUNN 87 AD63-32 44, 45, 47, 48, 49, 50, 52, 53, 54, 55, 57, 58, 59, 61, 62, ...
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Pin Descriptions (Continued) Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII). Symbol Pin No(s) Direction COL 170 CRS/SIGDET 169 MDC 138 MDIO 139 RXCLK/ 156 RXPMACLK1 RXD7, 166, RXD6, 165, RXD5, 164, RXD4, 163, RXD3, 160, ...
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Pin Descriptions (Continued) Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII). Symbol Pin No(s) Direction TXD7/MA15, 152, TXD6/MA14, 151, TXD5/MA13, 148, TXD4/MA12, 147, TXD3/MA11, 146, TXD2/MA10, 145, TXD1/MA9, 142, TXD0/MA8 141 TXEN/TXD8 153 TXER/TXD9 154 GTXCLK/ ...
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Pin Descriptions (Continued) BIOS ROM/Flash Interface Symbol Pin No(s) MWRN 94 MRDN 93 Note: DP83820 supports NM27LV010 for the ROM interface device. Clock Interface Symbol Pin No(s) Direction X1 122 X2 121 Phy And General Purpose Interface Symbol Pin ...
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Pin Descriptions (Continued) Serial EEPROM Interface Symbol Pin No(s) Direction EESEL 91 MA4/EECLK 109 MA3/EEDI 108 MD4/EEDO 101 Note: DP83820 supports NMC93C46 for the eeprom interface device. JTAG Interface Symbol Pin No(s) Direction TCK 178 TDI 181 TDO 180 ...
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Functional Description DP83820 consists of a PCI bus interface, BIOS ROM and EEPROM interfaces, Receive and Transmit Data Buffer PCI Bus Interface 32 32 93C06 Serial EEPROM Figure 3-1 3.1 DP83820 The DP83820 ...
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Functional Description 3.2 PCI Bus Interface The DP83820 implements the Peripheral Component Interconnect (PCI) bus interface as defined in PCI Local Bus Specification Version 2.2. When internal register are being accessed the DP83820 acts as a PCI target (slave). ...
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Functional Description If FRAMEN is asserted beyond the assertion of IRDYN, the DP83820 will still make data available as described above, but will also issue a Disconnect. That is, it will assert the CLK FRAMEN AD[31:0] Addr C/BEN[3:0] IRDYN ...
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Functional Description 3.3.3 Master Read A Master Read operation starts with the DP83820 asserting REQN. See Figure 3-6. If GNTN is asserted within 2 clock cycles, FRAMEN, Address, and Command will be generated 2 clocks after REQN (Address and ...
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Functional Description CLK FRAMEN AD[31:0] C/BEN[3:0] REQN GNTN IRDYN TRDYN DEVSELN PAR 3.3.5 Configuration Access Configuration register accesses are similar to Target reads and writes in that they are single data word transfers and are initiated by the system. ...
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Functional Description 3.4.5 Packet Recognition The Receive packet filter and recognition logic allows software to control which packets are accepted based on destination address and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. ...
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Functional Description 3.7.1 VLAN Tag Handling The Rx MAC can detect packets containing a 4-byte VLAN tag, and remove the VLAN tag from the received packet VLAN Tag removal is enabled, then the 4 bytes following the ...
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Functional Description 3.9 EEPROM Interface The DP83820 supports the attachment of an external EEPROM. The EEPROM interface provides the ability for the DP83820 to read from and write data to an external serial EEPROM device. Values in the external ...
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Functional Description RXFCSErrors RFC 1643, 802.3 LM RXMsdPktErrors RFC 1213, RFC 1643, 802.3 LM RXFAEErrors RFC 1643, 802.3 LM RXSymbolErrors 802.3 LM RXFrameTooLong RFC 1643, 802.3 LM RXIRLErrors 802.3 LM RXBadOpcodes 802.3 LM RXPauseFrames 802.3 LM TXOctetsOK RFC 1213, ...
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Functional Description TXPktsErrored RFC 1213 TXExcessiveCollisions RFC 1643, 802.3 LM TXExcessiveDeferral 802.3 LM TXOWC RFC 1643, 802.3 LM TXCSErrors RFC 1643, 802.3 LM TXSQEErrors RFC 1643 3.13 Buffer Management The buffer management scheme used on the DP83820 allows quick, ...
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Functional Description offset tag 0000h link 0004h or bufptr 0008h 0008h or cmdsts 0010h 000ch or extsts 0014h If 64-bit addressing is enabled, the link and bufptr fields are 64-bit fields. Otherwise, they are 32-bit fields. The DP83820 supports ...
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Functional Description 20 EC Excessive Collisions 19-16 CCNT Collision Count bit tag 26 RXA Receive Aborted 25 RXO Receive Overrun 24-23 DEST Destination Class 22 LONG Too Long Packet Received 21 RUNT Runt Packet Received 20 ISE Invalid Symbol ...
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Functional Description bit tag 31-22 21 UDPPKT UDP Packet 20 19 TCPPKT TCP Packet 18 17 IPPKT IP Packet 16 VPKT VLAN Packet 15-0 VTCI VLAN Tag Control Information bit tag 31-23 22 UDPERR UDP Checksum Error 21 UDPPKT ...
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Functional Description 3.13.2.1 Single Descriptor Packets To represent a packet in a single descriptor, the MORE bit in the cmdsts field is set to 0. 3.13.2.2 Multiple Descriptor Packets A single packet may also cross descriptor boundaries. This is ...
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Functional Description Descriptors Organized in a Ring (Recommended Method) addr 10100 10140 3.13.2.4 Descriptor Lists Descriptors may also be organized in linked lists using the link field. The linked list may be terminated by either a NULL link field, ...
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Functional Description 3.13.3 Transmit Architecture The Transmit architecture can support a single transmit queue, or can support multiple transmit queues for Figure 3-14 Transmit Architecture without Priority Queueing Transmit Descriptor link link bufptr bufptr cmdsts cmdsts Packet Packet Without ...
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Functional Description 3.13.3.1 Transmit State Machine The transmit state machine has the following states: txIdle txDescRefr txDescRead txFifoBlock txFragRead txDescWrite txAdvance The transmit state machine manipulates the following internal data spaces: TXDP CTDD TxDescCache descCnt fragPtr txFifoCnt txFifoAvail Inputs ...
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Functional Description txAdvance link != NULL link == NULL CR:TXEN && CTDD txDescRefr XferDone txAdvance XferDone txDescWrite 3.13.3.2 Transmit Data Flow without Priority Queueing In the DP83820 transmit architecture without Priority Queueing, packet transmission involves the following steps: 1. ...
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Functional Description was used to describe the packet, then completion status is updated only in the last descriptor. Intermediate descriptors only have the OWN bits modified the link field of the descriptor is non-zero, the state machine ...
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Functional Description Figure 3-18 Receive Architecture with Priority Queueing Receive Descriptor List link link Q0 bufptr bufptr cmdsts cmdsts link link Q1 bufptr bufptr cmdsts cmdsts link link Q2 bufptr bufptr cmdsts cmdsts link link Q3 bufptr bufptr cmdsts ...
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Functional Description FifoReady (rxPktCnt > (rxPktBytes > rxDrainThreshold) ... in other words have a complete packet in the FIFO (regardless of size), or the number of bytes that we do have is greater than the ...
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Functional Description CR:RXEN && CRDD rxDescRefr XferDone link = NULL rxAdvance XferDone rxDescWrite 3.13.5.1 Receive Data Flow without Priority Queueing With a bus mastering architecture, some number of buffers and descriptors for received packets must be pre-allocated when the ...
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Functional Description 3.13.5.2 Receive Data Flow with Priority Queueing With Priority Queueing still necessary to pre-allocate buffers and descriptors. Each priority queue must have a separate list of descriptors allocated. The receive data flow is similar to ...
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Register Set 4.1 Configuration Registers The DP83820 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the DP83820. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers ...
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Register Set (Continued) 4.1.2 Configuration Command and Status Register The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. The lower 16-bits (15-0) are devoted to command and are used to configure and control ...
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Register Set (Continued) 4.1.3 Configuration Revision ID Register This register stores the silicon revision number, revision number of software interface specification and lets the configuration software know that Ethernet controller in the class of network controllers. ...
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Register Set (Continued) 4.1.5 Configuration IO Base Address Register This register specifies the Base I/O address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication ...
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Register Set (Continued) 4.1.8 Configuration Subsystem Identification Register The CFGSID allows system software to distinguish between different subsystems based on the same PCI silicon. The values in this register can be loaded from the EEPROM if configuration is enabled. ...
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Register Set (Continued) 4.1.11 Configuration Interrupt Select Register This register stores the interrupt line number as identified by the POST software that is connected to the interrupt controller as well as DP83820 desired settings for maximum latency and minimum ...
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Register Set (Continued) 20 Reserved 19 PMEC PME Clock 18-16 PMV Power Management Version This bit field indicates compliance to a specific PM specification rev level. 15-8 NLIPTR Next List Item Pointer 7-0 CAPID Capability ID 4.1.13 Power Management ...
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Register Set (Continued) 4.2 Operational Registers The DP83820 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. When ...
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Register Set (Continued) CCh CCSR Clockrun Control/Status Register D0-DCh Reserved E0h TBICR TBI Control Register E4h TBISR TBI Status Register E8h TANAR TBI Auto-Negotiation Advertisement Register ECh TANLPAR TBI Auto-Negotiation Link Partner Ability Register F0h TANER TBI Auto-Negotiation Expansion ...
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Register Set (Continued) 4 TXR Transmit Reset 3 RXD Receiver Disable 2 RXE Receiver Enable 1 TXD Transmit Disable 0 TXE Transmit Enable 4.2.2 Configuration and Media Status Register This register allows configuration of a variety of device and ...
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Register Set (Continued) 16 MRM_DIS Memory Read Multiple Disable 15 MWI_DIS Memory Write and Invalidate Disable 14 T64ADDR Target 64-bit Addressing Enable 13 PCI64_DET PCI 64-bit Bus Detected 12 DATA64_EN 64-bit Data Enable 11 M64ADDR Master 64-bit Addressing Enable ...
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Register Set (Continued) 4.2.3 MII/EEPROM Access Register The MII/EEPROM Access Register provides an interface for software access to the serial management port of an external MII device or NMC9306 style EEPROM. The default values given assume that the MDIO ...
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Register Set (Continued) 4.2.4 EEPROM Map EEPROM Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh Registers for SOPAS[47:0] and PMATCH[47:0] can be accessed directly via the combination of the RFCR (offset 0048h) ...
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Register Set (Continued) 4.2.5 PCI Test Control Register Tag: PTSCR Offset: 000Ch bit tag 31-16 Reserved 15 Reserved 14 Reserved 13 RBIST_RST SRAM BIST Reset 12-11 Reserved 10 RBIST_EN SRAM BIST Enable 9 RBIST_DONE SRAM BIST Done 8 RBIST_RX1FAIL ...
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Register Set (Continued) 26 RXDESC3 Rx Descriptor for Priority Queue 3 25 RXDESC2 Rx Descriptor for Priority Queue 2 24 RXDESC1 Rx Descriptor for Priority Queue 1 23 RXDESC0 Rx Descriptor for Priority Queue 0 22 TXRCMP Transmit Reset ...
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Register Set (Continued) 4.2.7 Interrupt Mask Register This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting ...
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Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. Tag: IER Offset: 0018h bit tag description 31 Interrupt Enable 4.2.9 Interrupt Holdoff Register The Interrupt Holdoff Register prevents interrupt assertion ...
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Register Set (Continued) 4.2.11 Transmit Descriptor Pointer High Dword Register This register points to the upper 32-bits of the current Transmit Descriptor for 64-bit addressing. If Transmit Priority Queueing is enabled, this becomes the Descriptor pointer for all priority ...
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Register Set (Continued) 22-20 MXDMA Max DMA Burst Size per Tx DMA Burst 19 BRST_DIS 1000 Mb/s Burst Disable 18-16 15-8 FLTH Tx Fill Threshold 7-0 DRTH Tx Drain Threshold 4.2.13 General Purpose I/O Control Register This register allows ...
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Register Set (Continued) 5 GP1_OE General Purpose Pin 1 Output Enable 4 GP5_OUT General Purpose Pin 5 Output Value 3 GP4_OUT General Purpose Pin 4 Output Value 2 GP3_OUT General Purpose Pin 3 Output Value 1 GP2_OUT General Purpose ...
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Register Set (Continued) 4.2.16 Receive Configuration Register This register is used to set the receive configuration for DP83820. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here Tag: RXCFG Offset: ...
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Register Set (Continued) 5-1 DRTH Rx Drain Threshold 0 4.2.17 Priority Queueing Control Register This register allows control of Priority Queueing features. Tag: PQCR Offset: 003Ch bit tag description 31-4 3-2 RXPQ Receive Priority Queue Enable 1 TXFAIR Transmit ...
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Register Set (Continued) 4.2.18 Wake Command/Status Register The WCSR register is used to configure/control and monitor the DP83820 Wake On LAN logic. The Wake On LAN logic is used to monitor the incoming packet stream while in a low-power ...
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Register Set (Continued) 4.2.18.1 Wake on LAN The Wake on LAN logic provides several mechanisms for bringing the DP83820 out of a low-power state. Wake on ARP , Wake on Broadcast, Wake on Multicast Hash and Wake on Phy ...
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Register Set (Continued) 26 25-24 PS_STHI RX Stat FIFO Hi Threshold 23-22 PS_STLO RX Stat FIFO Lo Threshold 21-20 PS_FFHI RX Data FIFO Hi Threshold 19-18 PS_FFLO RX Data FIFO Lo Threshold 17 PS_TX Transmit Pause Frame 16 Reserved ...
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Register Set (Continued) 4.2.20 Receive Filter/Match Control Register The RFCR register is used to control and configure the DP83820 Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Tag: ...
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Register Set (Continued) 9-0 RFADDR Receive Filter Extended Register Address 4.2.21 Receive Filter/Match Data Register The RFDR register is used for reading from and writing to the internal receive filter registers, the pattern buffer memory, and the hash table ...
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Register Set (Continued) 4.2.22 Receive Filter Logic The Receive Filter Logic supports a variety of techniques for qualifying incoming packets. The most basic filtering options include Accept All Broadcast, Accept All Multicast and Accept All Unicast packets. These options ...
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Register Set (Continued) Pattern 3 Word 3Fh Pattern 3 Word 0 Pattern 2 Word 3Fh Pattern 2 Word 0 Pattern 1 Word 3Fh Pattern 1 Word 0 Pattern 0 Word 3Fh Pattern 0 Word 1 Pattern 0 Word 0 ...
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Register Set (Continued) 4.2.22.3 Accept on Multicast or Unicast Hash Multicast and Unicast addresses may be further qualified by use of the receive filter hash functions. An internal 2048 bit (256 byte) RAM-based hash table is used to perform ...
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Register Set (Continued) 4.2.23 Boot ROM Address Register The BRAR is used to setup the address for an access to an external ROM/FLASH device. Tag: BRAR Offset: 0050h bit tag description 31 AUTOINC Auto-Increment 30-16 15-0 ADDR Boot ROM ...
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Register Set (Continued) 4.2.26 Management Information Base Control Register The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of management information statistics. Tag: MIBC Offset: 005ch bit ...
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Register Set (Continued) 4.2.27 Management Information Base Registers The counters provide a set of statistics compliant with the following management specifications: MIB II, Ether-like MIB, and IEEE MIB. The values provided are accessed through the various registers as shown ...
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Register Set (Continued) 4.2.28 Transmit Descriptor Pointer 1 Register This register points to the Transmit Descriptor for Priority Queue 1. Tag: TXDP1 Offset: 00A0h bit tag description 31-3 TXDP1 Transmit Descriptor Pointer 1 2-0 4.2.29 Transmit Descriptor Pointer 2 ...
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Register Set (Continued) 4.2.31 Receive Descriptor Pointer 1 Register This register points to the Receive Descriptor for Priority Queue 1. Tag: RXDP1 Offset: 00B0h bit tag description 31-3 RXDP1 Receive Descriptor Pointer 1 2-0 4.2.32 Receive Descriptor Pointer 2 ...
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Register Set (Continued) 4.2.33 Receive Descriptor Pointer 3 Register This register points to the Receive Descriptor for Priority Queue 3 (highest priority). Tag: RXDP3 Offset: 00B8h bit tag description 31-3 RXDP3 Receive Descriptor Pointer 3 2-0 4.2.34 VLAN/IP Receive ...
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Register Set (Continued) 4.2.35 VLAN/IP Transmit Control Register This register allows enabling of the various VLAN tag handling features and IP checksum offload features. Tag: VTCR Offset: 00C0h bit tag description 31-4 3 PPCHK Per-Packet Checksum Generation 2 GCHK ...
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Register Set (Continued) 4.2.38 TBI Control Register This register is used to enable and/or restart TBI auto-negotiation also used to enable PCS loopback of TBI data. Tag: TBICR Offset: 00E0h bit tag 15 14 MR_LOOPBACK TBI PCS ...
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Register Set (Continued) 13-12 RF2, RF1 Remote Fault 11-9 8-7 PS2, PS1 Pause Capability Encoding PS1 indicates that the device is capable of providing symmetric 6 HALF_DUP Half Duplex 5 FULL_DUP Full Duplex 4-0 4.2.41 TBI Auto-Negotiation Link Partner ...
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Register Set (Continued) 4.2.42 TBI Auto-Negotiation Expansion Register This register is a read-only register indicating if a new base page from the link partner has been received and if the local device is next page able. Writes to this ...
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DC and AC Specifications Absolute Maximum Ratings Supply Voltage ( 3.3 V PCI signaling, 5.0 V tolerant DC Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Power Dissipation ...
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DC and AC Specifications 5.2 AC Specifications 5.2.1 PCI Clock Timing PCICLK Number PCICLK Low Time 5.2.1.1 PCICLK High Time 5.2.1.2 PCICLK Cycle Time 5.2.1.3 5.2.2 X1 Clock Timing X1 Number X1 Low Time 5.2.2.1 X1 High Time 5.2.2.2 ...
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DC and AC Specifications 5.2.3 Power On Reset (PCI Active) Power Stable RSTN PCICLK Number RSTN Active Duration from PCICLK 5.2.3.1 stable Reset Disable to 1st PCI Cycle 5.2.3.2 EE Enabled EE Disabled Note 1: Minimum reset complete time ...
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DC and AC Specifications 5.2.5 POR PCI Inactive VDD T1 EESEL Number VDD stable to EE access 5.2.5.1 VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. 5.2.6 PCI Bus Cycles The following ...
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DC and AC Specifications PCI Configuration Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] Addr C/BEN[3:0] Cmd IDSEL T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Configuration Write PCICLK T1 T2 FRAMEN ...
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DC and AC Specifications PCI Bus Master Read PCICLK T3 T3 FRAMEN T3 T3 REQ64N T4 T3 AD[63:0] Addr T3 T3 Cmd C/BEN[7:0] IRDYN TRDYN STOPN DEVSELN ACK64N PAR PAR64 PERRN (Continued ...
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DC and AC Specifications PCI Bus Master Write PCICLK T3 FRAMEN T3 REQ64N T3 AD[63:0] Addr T3 C/BEN[7:0] Cmd IRDYN TRDYN STOPN DEVSELN ACK64N PAR PAR64 PERRN (Continued Data ...
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DC and AC Specifications PCI Target Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] Addr C/BEN[3:0] Cmd BE T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Target Write PCICLK T1 T2 FRAMEN ...
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DC and AC Specifications PCI Bus Master Burst Read PCICLK T3 FRAMEN T3 REQ64N T4 T3 AD[63:0] Addr T3 T3 Cmd C/BEN[7:0] IRDYN TRDYN STOPN DEVSELN ACK64N PAR PAR64 PERRN (Continued Data Data ...
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DC and AC Specifications PCI Bus Master Burst Write PCICLK T3 FRAMEN T3 REQ64N T3 AD[63:0] Addr T3 C/BEN[7:0] Cmd IRDYN TRDYN STOPN DEVSELN ACK64N PAR PAR64 PERRN PCI Bus Arbitration PCICLK T3 REQN GNTN (Continued ...
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DC and AC Specifications 5.2.7 RX MII/GMII Interface RXCLK RXDV RXER RXD Number RXDV/RXER/RXD to RXCLK Setup 5.2.7.1 Requirement RXDV/RXER/RXD to RXCLK Hold 5.2.7.2 Requirement 5.2.8 RX TBI Interface RXPMA CLK0 RXPMA CLK1 RXD Number RXD[9:0] to RXPMACLK0 or ...
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DC and AC Specifications 5.2.9 TX MII Interface TXCLK TXEN TXD Number TXEN/TXD Output Delay from TXCLK 5.2.9.1 5.2.10 TX GMII/TBI Interface GTXCLK TXEN TXD TXER Number TXEN/TXER/TXD Output Delay from 5.2.10.1 GTXCLK (Continued Parameter Min 2 ...
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DC and AC Specifications 5.2.11 EEPROM Auto-Load EECLK EESEL EEDO EEDI Number EECLK Cycle Time 5.2.11.1 EECLK Delay from EESEL 5.2.11.2 EECLK Low to EESEL Invalid 5.2.11.3 EECLK to EEDO Valid 5.2.11.4 EEDI Setup Time to EECLK 5.2.11.5 EEDI ...
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DC and AC Specifications 5.2.12 Boot PROM/FLASH T5 T16 MCSN MRDN T3 MA[15:0] MD[7:0] MWRN Number Data Valid to MRDN Invalid 5.2.12.1 Data Invalid from MRDN Invalid 5.2.12.2 Address Valid to MRDN 5.2.12.3 Address Invalid from MRDN Invalid 5.2.12.4 ...
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DC and AC Specifications 5.2.13 JTAG Timing TCK TDO (output) TCK TDI, TMS (input) TCK non-test inputs TCK non-test outputs Number TCK Period 5.2.13.1 TCK low/high time 5.2.13.2 TCK to TDO (Output) Delay Time 5.2.13.3 TDI, TMS (Input) to ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...