PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 117

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 10-3:
© 2006 Microchip Technology Inc.
RB0/AN12/
INT0/FLT0/
SDI/SDA
RB1/AN10/
INT1/SCK/
SCL
RB2/AN8/
INT2/VMO
RB3/AN9/
CCP2/VPO
RB4/AN11/
KBI0/CSSPP
RB5/KBI1/
PGM
Legend:
Note 1:
Pin
2:
3:
4:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I
overridden for this option)
Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD operation is enabled.
40/44-pin devices only.
2
C/SMB = I
CSSPP
Function
CCP2
AN12
AN10
PORTB I/O SUMMARY
AN11
INT0
FLT0
INT1
INT2
VMO
KBI0
KBI1
PGM
SDA
SCK
VPO
RB0
RB1
SCL
RB2
AN8
RB3
AN9
RB4
RB5
SDI
2
(2)
(4)
C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
Setting
TRIS
0
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
0
1
1
1
0
0
1
1
0
1
0
0
1
1
1
0
0
1
1
x
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O Type
I
I
PIC18F2455/2550/4455/4550
2
2
C/SMB I
C/SMB I
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATB<0> data output; not affected by analog input.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 12.
External interrupt 0 input.
Enhanced PWM Fault input (ECCP1 module); enabled in software.
SPI data input (MSSP module).
I
LATB<1> data output; not affected by analog input.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 10.
External interrupt 1 input.
SPI clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
I
LATB<2> data output; not affected by analog input.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 8.
External interrupt 2 input.
External USB transceiver VMO data output.
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 9.
CCP2 Compare and PWM output.
CCP2 Capture input.
External USB transceiver VPO data output.
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
A/D input channel 11.
Interrupt-on-pin change.
SPP chip select control output.
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-pin change.
Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
2
2
2
2
C™ data output (MSSP module); takes priority over port data.
C data input (MSSP module); input type depends on module setting.
C clock output (MSSP module); takes priority over port data.
C clock input (MSSP module); input type depends on module setting.
(1)
(1)
(1)
(1)
(1)
Description
(1)
(1)
(1)
(1)
(1)
DS39632C-page 115