PIC18F4550-I/P Microchip Technology Inc., PIC18F4550-I/P Datasheet - Page 193

• Manufacturer Part Number: PIC18F4550-I/P
• Description: 40 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4550-I/P

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 34
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.3.3
Reading from the SPP involves reading the SPPDATA
register. Reading the register the first time initiates the
read operation. When the read is finished, indicated by
the SPPBUSY bit, the SPPDATA will be loaded with the
current data.
The following is an example read sequence:
1.
2.
REGISTER 18-3:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
RDSPP
Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address. If address write is not used then skip to
step 3.
Monitor the SPPBUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
R-0
READING FROM THE SPP
RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a read from the SPP
0 = The last transaction was not a read from the SPP
WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a write to the SPP
0 = The last transaction was not a write to the SPP
Unimplemented: Read as ‘0’
SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request
ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
•
•
0001
0000 = Endpoint Address 0
WRSPP
R-0
SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER
W = Writable bit
‘1’ = Bit is set
•
•
U-0
—
PIC18F2455/2550/4455/4550
SPPBUSY
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADDR3
R/W-0
3.
4.
5.
Read the data from the SPPDATA register; the
data from the previous read operation is
returned. The SPP automatically starts the read
cycle for the next read.
Monitor the SPPBUSY bit to determine when the
data has been read. The duration depends on
the wait states.
Go back to step 3 to read the current byte from
the SPP and start the next read cycle.
ADDR2
R/W-0
x = Bit is unknown
ADDR1
R/W-0
DS39632C-page 191
ADDR0
R/W-0
bit 0