PIC16F684-I/P

Manufacturer Part NumberPIC16F684-I/P
Description14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
ManufacturerMicrochip Technology Inc.
PIC16F684-I/P datasheet
 


Specifications of PIC16F684-I/P

A/d Inputs8-Channel, 10-BitComparators2
Cpu Speed5 MIPSEeprom Memory256 Bytes
Input Output12Memory TypeFlash
Number Of Bits8Package Type14-pin PDIP
Programmable Memory3.5K BytesRam Size128 Bytes
Speed20 MHzTimers2-8-bit, 1-16-bit
Voltage, Range2-5.5 VLead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device
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PIC16F684
Data Sheet
14-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
© 2006 Microchip Technology Inc.
DS41202D

PIC16F684-I/P Summary of contents

  • Page 1

    ... Microchip Technology Inc. PIC16F684 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41202D ...

  • Page 2

    ... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2006 Microchip Technology Inc. ...

  • Page 3

    ... Flash/Data EEPROM retention: > 40 years Program Memory Device Flash (words) PIC16F684 2048 © 2006 Microchip Technology Inc. PIC16F684 Low-Power Features: • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 220 MHz, 2.0V, typical • Watchdog Timer Current 2.0V, typical Peripheral Features: • ...

  • Page 4

    ... PIC16F684 14-Pin Diagram (PDIP, SOIC, TSSOP) RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/P1C TABLE 1: DUAL IN-LINE PIN SUMMARY I/O Pin Analog Comparators RA0 13 AN0 C1IN+ RA1 12 AN1/V C1IN- REF RA2 11 AN2 C1OUT (1) RA3 4 — — RA4 3 AN3 — RA5 2 — — RC0 ...

  • Page 5

    ... P1D — — P1C — — P1B — — CCP1/P1A — — — — — — — PIC16F684 /ICSPCLK REF Basic Y ICSPDAT/ULPWU Y ICSPCLK Y — (2) Y MCLR OSC2/CLKOUT Y OSC1/CLKIN — — — — — — ...

  • Page 6

    ... PIC16F684 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 19 4.0 I/O Ports ..................................................................................................................................................................................... 31 5.0 Timer0 Module ........................................................................................................................................................................... 43 6.0 Timer1 Module with Gate Control............................................................................................................................................... 47 7.0 Timer2 Module ........................................................................................................................................................................... 53 8.0 Comparator Module.................................................................................................................................................................... 55 9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 65 10.0 Data EEPROM Memory ............................................................................................................................................................. 75 11 ...

  • Page 7

    ... DEVICE OVERVIEW The PIC16F684 is covered by this data sheet available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages. Figure 1-1 shows a block diagram of the PIC16F684 device. Table 1-1 shows the pinout description. FIGURE 1-1: PIC16F684 BLOCK DIAGRAM Configuration Flash Program Memory ...

  • Page 8

    ... PIC16F684 TABLE 1-1: PIC16F684 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT/ULPWU ICSPDAT RA1/AN1/C1IN-/V /ICSPCLK REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/V PP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C2IN- RC2/AN6/P1D RC3/AN7/P1C RC4/C2OUT/P1B RC5/CCP1/P1A Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL DS41202D-page 6 Input Output Type Type ...

  • Page 9

    ... Program Memory Organization The PIC16F684 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC16F684 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...

  • Page 10

    ... PIC16F684 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the PIC16F684. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1) ...

  • Page 11

    ... TABLE 2-1: PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...

  • Page 12

    ... PIC16F684 TABLE 2-2: PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) ...

  • Page 13

    ... Status bits. For other instructions not affect- ing any Status bits, see Section 13.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC16F684 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...

  • Page 14

    ... PIC16F684 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External RA2/INT interrupt • Timer0 • Weak pull-ups on PORTA REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RAPU INTEDG ...

  • Page 15

    ... GIE of the INTCON register. User software appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 INTE RAIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) PIC16F684 should ensure the R/W-0 R/W-0 INTF RAIF bit Bit is unknown DS41202D-page 13 ...

  • Page 16

    ... PIC16F684 2.2.2.4 PIE1 Register The PIE1 register contains the peripheral interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...

  • Page 17

    ... GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 C2IF C1IF OSFIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41202D-page 15 ...

  • Page 18

    ... PIC16F684 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-2) contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR ...

  • Page 19

    ... Table Read” (DS00556). © 2006 Microchip Technology Inc. 2.3.2 STACK The PIC16F684 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...

  • Page 20

    ... PIC16F684 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F684 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...

  • Page 21

    ... INTOSC 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 31 kHz 000 Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) PIC16F684 /4 output OSC is a calibrated FOSC<2:0> SCS<0> System Clock (CPU and Peripherals) DS41202D-page 19 ...

  • Page 22

    ... PIC16F684 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...

  • Page 23

    ... Clock Cycles (OST) 125 kHz to 8 MHz 1 s (approx.) FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Clock from Ext. System I/O Note 1: Alternate pin functions are listed in the Section 1.0 “Device Overview”. PIC16F684 ) WARM OSC1/CLKIN ® PICmicro MCU (1) OSC2/CLKOUT DS41202D-page 21 ...

  • Page 24

    ... PIC16F684 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...

  • Page 25

    ... System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. PIC16F684 (High-Frequency Internal (Low-Frequency Internal 000. Then, set the ...

  • Page 26

    ... PIC16F684 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...

  • Page 27

    ... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2006 Microchip Technology Inc. PIC16F684 3.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6) ...

  • Page 28

    ... PIC16F684 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC IRCF <2:0> 0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF <2:0> ...

  • Page 29

    ... OSTS bit of the OSCCON register to remain clear. © 2006 Microchip Technology Inc. PIC16F684 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...

  • Page 30

    ... PIC16F684 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP ...

  • Page 31

    ... Fail-Safe circuit is not active Clock during oscillator start-up (i.e., after exiting Failure Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock completed. PIC16F684 switchover has successfully DS41202D-page 29 ...

  • Page 32

    ... PIC16F684 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...

  • Page 33

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R-1 R/W-1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 INITIALIZING PORTA ;Bank 0 ;Init PORTA ;Set RA<2:0> to ;digital I/O ;Bank 1 ;digital I/O ;Set RA<3:2> as inputs ;and set RA<5:4,1:0> ...

  • Page 34

    ... PIC16F684 4.2 Additional Pin Functions Every PORTA pin on the PIC16F684 has an interrupt-on-change option and a weak pull-up option. RA0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘ ...

  • Page 35

    ... WPUA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 IOCA4 IOCA3 IOCA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 R/W-1 R/W-1 WPUA1 WPUA0 bit Bit is unknown R/W-0 R/W-0 IOCA1 IOCA0 bit Bit is unknown ...

  • Page 36

    ... PIC16F684 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-Up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0 ...

  • Page 37

    ... ADC • In-Circuit Serial Programming clock (1) Analog Input Mode RAPU - + 0 1 (1) Analog Input Mode ULPWUE PORTA To Comparator To A/D Converter PIC16F684 /ICSPCLK REF V DD Weak V DD I/O Pin ULP V SS DS41202D-page 35 ...

  • Page 38

    ... PIC16F684 FIGURE 4-2: BLOCK DIAGRAM OF RA1 (1) Analog Input Mode Data Bus WPUA RAPU RD WPUA PORTA TRISA (1) Analog Input Mode RD TRISA RD PORTA IOCA EN RD IOCA Interrupt-on- Change RD PORTA To Comparator To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. DS41202D-page 36 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT Figure 4-3 shows the diagram for this pin ...

  • Page 39

    ... TRISA RD PORTA IOCA RD IOCA Interrupt-on- Change To T1G To A/D Converter Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. PIC16F684 BLOCK DIAGRAM OF RA4 (3) Analog Input Mode (1) CLK Modes Weak RAPU Oscillator Circuit OSC1 ...

  • Page 40

    ... PIC16F684 4.2.5.6 RA5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF RA5 INTOSC Mode TMR1LPEN ...

  • Page 41

    ... PSA PS2 PS1 RA4 RA3 RA2 RA1 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 WPUA4 — WPUA2 WPUA1 WPUA0 PIC16F684 Value on Value on: Bit 0 all other POR, BOR Resets ANS0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 BOR --01 --qq --0u --uu RAIF 0000 0000 ...

  • Page 42

    ... PIC16F684 4.3 PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D Converter (ADC) or Comparator. For specific information about individual functions such as the Enhanced CCP or the ADC, refer to the appropriate section in this data sheet. ...

  • Page 43

    ... Enhanced CCP FIGURE 4-8: Data Bus PORTC I/O Pin TRISC SS RD TRISC RD PORTC To A/D Converter Note 1: Analog Input mode comes from ANSEL. PIC16F684 BLOCK DIAGRAM OF RC2 AND RC3 CCPOUT Enable V DD CCPOUT 1 0 I/O Pin V SS Analog Input (1) Mode DS41202D-page 41 ...

  • Page 44

    ... PIC16F684 4.3.5 RC4/C2OUT/P1B The RC4 is configurable to function as one of the following: • a general purpose I/O • a digital output from the comparator • a digital output from the Enhanced CCP Note: Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results. Therefore, if C2OUT is enabled, the ECCP can not be used in Half-Bridge or Full-Bridge mode and vice-versa ...

  • Page 45

    ... The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. 8-bit Prescaler PSA 8 3 PS<2:0> 16-bit 16 PSA WDTPS<3:0> PIC16F684 Data Bus 8 1 Sync 2 TMR0 cycles 0 Set Flag bit T0IF on Overflow 1 WDT Time-out ...

  • Page 46

    ... PIC16F684 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...

  • Page 47

    ... Bit 4 Bit 3 Bit 2 Bit 1 INTE RAIE T0IF INTF T0SE PSA PS2 PS1 PIC16F684 R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown Value on Value on: Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu RAIF 0000 0000 0000 0000 ...

  • Page 48

    ... PIC16F684 NOTES: DS41202D-page 46 © 2006 Microchip Technology Inc. ...

  • Page 49

    ... When TMR1CS = 1, the clock source is OSC supplied externally. Clock Source F /4 OSC T1CKI pin TMR1ON To C2 Comparator Module Timer1 Clock ( TMR1L 1 T1SYNC * 1 Prescaler OSC 0 Internal Clock T1CKPS<1:0> TMR1CS PIC16F684 TMR1CS 0 1 TMR1GE T1GINV Synchronized clock input Synchronize (2) det C2OUT T1GSS DS41202D-page 47 ...

  • Page 50

    ... PIC16F684 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples determined by the Timer1 prescaler. OSC 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. ...

  • Page 51

    ... If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). © 2006 Microchip Technology Inc. PIC16F684 6.9 ECCP Capture/Compare Time Base The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...

  • Page 52

    ... PIC16F684 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module ...

  • Page 53

    ... T1GSS INTE RAIE T0IF INTF C2IE C1IE OSFIE TMR2IE C2IF C1IF OSFIF TMR2IF T1CKPS0 T1OSCEN T1SYNC TMR1CS PIC16F684 Value on Value on: Bit 0 all other POR, BOR Resets C2SYNC ---- --10 ---- --10 RAIF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IF 0000 0000 ...

  • Page 54

    ... PIC16F684 NOTES: DS41202D-page 52 © 2006 Microchip Technology Inc. ...

  • Page 55

    ... A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written. TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 TOUTPS<3:0> PIC16F684 Sets Flag bit TMR2IF DS41202D-page 53 ...

  • Page 56

    ... PIC16F684 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...

  • Page 57

    ... Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2006 Microchip Technology Inc. PIC16F684 8.1 Comparator Overview A comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at V ...

  • Page 58

    ... PIC16F684 FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM C1INV C1 Note 1: Q1 and Q3 are phases of the four-phase system clock ( held high during Sleep mode. FIGURE 8-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2INV C2 Note 1: Comparator output is latched on falling edge of Timer1 clock source and Q3 are phases of the four-phase system clock ( held high during Sleep mode ...

  • Page 59

    ... Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog SS and the DD 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified 0. LEAKAGE V 0.6V T ±500 nA Vss PIC16F684 IC To ADC Input DS41202D-page 57 ...

  • Page 60

    ... PIC16F684 8.2 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 8-5. I/O lines change as a function of the mode and are designated as follows: • Analog function (A): digital input buffer is disabled • ...

  • Page 61

    ... PIR1 register will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of CMCON0. This will end the mismatch condition. b) Clear the CxIF interrupt flag. PIC16F684 all writes include a read DS41202D-page 59 ...

  • Page 62

    ... PIC16F684 A persistent mismatch condition will preclude clearing the CxIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CxIF bit to be cleared. FIGURE 8-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ Q1 Q3 CxIN CxOUT Set CMIF (level) CMIF FIGURE 8-7: ...

  • Page 63

    ... Two common reference comparators with outputs 111 = Comparators off. CxIN pins are configured as digital I/O © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 C1INV CIS CM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - PIC16F684 R/W-0 R/W-0 CM1 CM0 bit Bit is unknown DS41202D-page 61 ...

  • Page 64

    ... PIC16F684 8.8 Comparator C2 Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details ...

  • Page 65

    ... Voltage Reference can be found in Section 15.0 “Electrical Specifications”. U-0 R/W-0 R/W-0 — VR3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared drain and REF SS VR<3:0> 15) = (VR<3:0>/24 (VR<3:0>/32 PIC16F684 CV OUTPUT VOLTAGE REF = (VR<3:0>/24 (VR<3:0> V /32 / cannot be realized due module current. REF ...

  • Page 66

    ... PIC16F684 FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16-1 Analog MUX VREN REF Comparator 2 Input 1 0 (1) VR<3:0> TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 ANSEL ANS7 ANS6 ANS5 CMCON0 C2OUT C1OUT C2INV CMCON1 — ...

  • Page 67

    ... Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM RA0/AN0 RA1/AN1/V REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 CHS <3:0> © 2006 Microchip Technology Inc. (ADC) allows V DD VCFG = 0 V REF VCFG = 1 A/D GO/DONE ADFM ADON PIC16F684 Left Justify 1 = Right Justify 10 ADRESH ADRESL DS41202D-page 65 ...

  • Page 68

    ... PIC16F684 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...

  • Page 69

    ... The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-4 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result PIC16F684 ADRESL bit 0 Unimplemented: Read as ‘ ...

  • Page 70

    ... PIC16F684 9.2 ADC Operation 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the analog-to-digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “ ...

  • Page 71

    ... BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2006 Microchip Technology Inc. PIC16F684 DS41202D-page 69 ...

  • Page 72

    ... PIC16F684 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 ADFM VCFG — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit ...

  • Page 73

    ... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x ADRES4 ADRES3 ADRES2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 R/W-x R/W-x ADRES3 ADRES2 bit Bit is unknown R/W-x R/W-x — — bit Bit is unknown ...

  • Page 74

    ... PIC16F684 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (R ) and the internal sampling switch (R ...

  • Page 75

    ... REF © 2006 Microchip Technology Inc Sampling Switch Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale REF Transition PIC16F684 HOLD REF Sampling Switch (k ) DS41202D-page 73 ...

  • Page 76

    ... PIC16F684 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG — ADCON1 — ADCS2 ADCS1 ANSEL ANS7 ANS6 ANS5 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte INTCON GIE PEIE T0IE PIE1 EEIE ...

  • Page 77

    ... EECON2 (not a physically implemented register) • EEDAT • EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC16F684 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 ...

  • Page 78

    ... PIC16F684 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non-implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation ...

  • Page 79

    ... EEPROM. The WREN bit is not cleared by hardware. © 2006 Microchip Technology Inc. PIC16F684 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...

  • Page 80

    ... PIC16F684 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) EEPROM write. ...

  • Page 81

    ... TABLE 11-1: ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Capture Compare PWM R/W-0 R/W-0 R/W-0 DC1B0 CCP1M3 CCP1M2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit Bit is unknown DS41202D-page 79 ...

  • Page 82

    ... PIC16F684 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...

  • Page 83

    ... TMR1IF of the PIR1 register. 2: Removing changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. PIC16F684 the match condition by DS41202D-page 81 ...

  • Page 84

    ... PIC16F684 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...

  • Page 85

    ... PIC16F684 PULSE WIDTH = CCPR1L:CCP1CON<5:4> T (TMR2 Prescale Value) OSC DUTY CYCLE RATIO CCPR1L:CCP1CON<5:4> = ---------------------------------------------------------------------- - 4 PR2 + bits of OSC PWM RESOLUTION log 4 PR2 ...

  • Page 86

    ... PIC16F684 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...

  • Page 87

    ... PWM signal. P1M<1:0> CCP1M<3:0> CCP1/P1A TRIS P1B TRIS Output Q Controller P1C TRIS S P1D TRIS PWM1CON CCP1/P1A P1B Yes No Yes Yes Yes Yes Yes Yes PIC16F684 prevent the generation of an CCP1/P1A P1B P1C P1D P1C P1D Yes Yes Yes Yes DS41202D-page 85 ...

  • Page 88

    ... PIC16F684 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active P1B Inactive (Full-Bridge, 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive Relationships: • ...

  • Page 89

    ... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay mode”). © 2006 Microchip Technology Inc. PIC16F684 Pulse 0 Width Period (1) (1) Delay Delay PR2+1 ...

  • Page 90

    ... PIC16F684 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-16). This mode can be used for half-bridge ...

  • Page 91

    ... PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 11-10: EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2006 Microchip Technology Inc FET Driver Load FET Driver QB V- PIC16F684 QC FET Driver FET Driver QD DS41202D-page 89 ...

  • Page 92

    ... PIC16F684 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41202D-page 90 Period (1) Period (1) © ...

  • Page 93

    ... Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. (1) Period Pulse Width (2) PIC16F684 Period DS41202D-page 91 ...

  • Page 94

    ... PIC16F684 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE P1A P1B P1C P1D External Switch C External Switch D Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. ...

  • Page 95

    ... Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC16F684 R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown DS41202D-page 93 ...

  • Page 96

    ... PIC16F684 Note 1: The auto-shutdown condition level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period ...

  • Page 97

    ... Period Pulse Width (2) P1A td (2) P1B destructive ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. for V+ FET Driver P1A Load FET Driver P1B V- PIC16F684 EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period td (1) ( DS41202D-page 95 ...

  • Page 98

    ... PIC16F684 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away ...

  • Page 99

    ... SPECIAL FEATURES OF THE CPU The PIC16F684 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...

  • Page 100

    ... PIC16F684 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — bit 15 CPD CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled ...

  • Page 101

    ... Word is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41244) and thus, does not require reprogramming. 12.3 Reset The PIC16F684 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation ...

  • Page 102

    ... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC16F684 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...

  • Page 103

    ... Power-up Timer will be re-initialized. Once V rises above V BOR 64 ms Reset. 12.3.5 BOR CALIBRATION The PIC16F684 stores the BOR calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified Word “PIC12F6XX/16F6XX Memory Programming Specifi- cation” ...

  • Page 104

    ... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC16F684 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...

  • Page 105

    ... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2006 Microchip Technology Inc. PIC16F684 T PWRT T OST T PWRT T OST ) DD T PWRT T OST DS41202D-page 103 ...

  • Page 106

    ... PIC16F684 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx (6) PORTA 05h --x0 x000 (6) PORTC 07h --xx 0000 PCLATH ...

  • Page 107

    ... Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution © 2006 Microchip Technology Inc. PIC16F684 Wake-up from Sleep through MCLR Reset WDT Reset (Continued) Wake-up from Sleep through ...

  • Page 108

    ... PIC16F684 12.4 Interrupts The PIC16F684 has 11 sources of interrupt: • External Interrupt RA2/INT • Timer0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...

  • Page 109

    ... Some peripherals depend upon the system clock for operation. Since the system clock is suspended during Sleep, only those peripherals which do not depend upon the system clock will wake the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”. PIC16F684 The interrupt can ...

  • Page 110

    ... PIC16F684 FIGURE 12-8: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF flag (5) (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3 the same whether Inst (PC single cycle or a 2-cycle instruction. ...

  • Page 111

    ... Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F684 does not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR ...

  • Page 112

    ... WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC16F684 Section 5.0 “Timer0 Module” for more information. 0 From Timer0 Clock Source ...

  • Page 113

    ... Bit is cleared (1) Bit 4 Bit 3 Bit 2 Bit 1 WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 FOSC1 PIC16F684 R/W-0 R/W-0 WDTPS0 SWDTEN bit Bit is unknown Value on Value on: Bit 0 all other POR, BOR Resets ---0 1000 PS0 1111 1111 ...

  • Page 114

    ... PIC16F684 12.7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance) ...

  • Page 115

    ... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2006 Microchip Technology Inc OST (2) T (3) Interrupt Latency Processor in Sleep Inst( Inst( Dummy Cycle not been PIC16F684 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) DS41202D-page 113 ...

  • Page 116

    ... A special debugging adapter allows the ICD device to be used in place of a PIC16F684 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F684 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...

  • Page 117

    ... INSTRUCTION SET SUMMARY The PIC16F684 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...

  • Page 118

    ... PIC16F684 TABLE 13-2: PIC16F684 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...

  • Page 119

    ... Operands: Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSC Syntax: k Operands: Operation: Status Affected: Description: f,d PIC16F684 Bit Clear f [ label ] BCF f 127 (f<b>) 0 None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f 127 ...

  • Page 120

    ... PIC16F684 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...

  • Page 121

    ... The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2006 Microchip Technology Inc. PIC16F684 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d ...

  • Page 122

    ... PIC16F684 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...

  • Page 123

    ... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2006 Microchip Technology Inc. PIC16F684 RETLW Return with literal in W Syntax: [ label ] RETLW k Operands 255 Operation: k (W); TOS PC Status Affected: ...

  • Page 124

    ... PIC16F684 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...

  • Page 125

    ... Syntax: Operands: Operation: Status Affected: Description: f<3:0> f<3:0> XORWF Syntax: Operands: Operation: Status Affected: Description: PIC16F684 Exclusive OR literal with W [ label ] XORLW 255 (W) .XOR The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. ...

  • Page 126

    ... PIC16F684 NOTES: DS41202D-page 124 © 2006 Microchip Technology Inc. ...

  • Page 127

    ... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC16F684 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...

  • Page 128

    ... PIC16F684 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...

  • Page 129

    ... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC16F684 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

  • Page 130

    ... PIC16F684 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages pins. ...

  • Page 131

    ... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. ........................................................................... -0. – ∑ DIS PIC16F684 + 0.3V ∑ {( ∑(V – DS41202D-page 129 ...

  • Page 132

    ... PIC16F684 FIGURE 15-1: PIC16F684 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 2.0 2.5 DS41202D-page 130 8 10 Frequency (MHz) ± ...

  • Page 133

    ... DC Characteristics: PIC16F684-I (Industrial) PIC16F684-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure VDD DD internal Power-on Reset signal * These parameters are characterized but not tested ...

  • Page 134

    ... PIC16F684 15.2 DC Characteristics: PIC16F684-I (Industrial) PIC16F684-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( D011* D012 D013* D014 D015 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 135

    ... DC Characteristics: PIC16F684-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2) Current D021 D022 D023 D024 D025* D026 D027 * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 136

    ... PIC16F684 15.4 PIC16F684 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2) Current ( D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

  • Page 137

    ... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC16F684-I (Industrial) PIC16F684-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

  • Page 138

    ... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. DS41202D-page 136 PIC16F684-I (Industrial) PIC16F684-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

  • Page 139

    ... QFN 4x0.9mm package 32.5 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 31.7 C/W 14-pin TSSOP package 2.6 C/W 16-pin QFN 4x0.9mm package 150 C For derated power calculations — — INTERNAL (NOTE 1) — — DER (NOTE DER PIC16F684 Conditions + P / INTERNAL DS41202D-page 137 ...

  • Page 140

    ... PIC16F684 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings Fall ...

  • Page 141

    ... AC Characteristics: PIC16F684 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C T Param Sym Characteristic No. OS01 F External CLKIN Frequency OSC (1) Oscillator Frequency ...

  • Page 142

    ... PIC16F684 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 T Fail-Safe Sample Clock SC (1) Period OS08 HF Internal Calibrated OSC HFINTOSC Frequency OS09* LF Internal Uncalibrated OSC LFINTOSC Frequency ...

  • Page 143

    ... OS13 OS17 OS15 OS18, OS19 +125°C Min (1) — (1) — (1) — ( 200 ns OSC — 50 (Q2 cycle) 20 OSC (2) — — (2) — — PIC16F684 Execute Q3 OS12 OS18 OS14 New Value Typ† Max Units Conditions — 5.0V DD — 5.0V DD — — — 70* ...

  • Page 144

    ... PIC16F684 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...

  • Page 145

    ... All specified values and V must be capacitively decoupled as close to the device PIC16F684 Conditions 5V, -40°C to +85° 5V, -40°C to +85° ...

  • Page 146

    ... PIC16F684 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width ...

  • Page 147

    ... Microchip Technology Inc. CC01 CC02 CC03 +125°C Min No Prescaler 0. With Prescaler 20 No Prescaler 0. With Prescaler PIC16F684 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — prescale value ( 16) ...

  • Page 148

    ... PIC16F684 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristics No. CM01 V Input Offset Voltage OS CM02 V Input Common Mode Voltage CM CM03* C Common Mode Rejection Ratio MRR CM04* T Response Time RT CM05 Comparator Mode Change Output Valid * These parameters are characterized but not tested ...

  • Page 149

    ... TABLE 15-9: PIC16F684 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD01 N Resolution R AD02 E Integral Error IL AD03 E Differential Error DL AD04 E Offset Error OFF AD07 E Gain Error GN (3) AD06 V Reference Voltage REF AD06A AD07 ...

  • Page 150

    ... PIC16F684 TABLE 15-10: PIC16F684 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T Amplifier Settling Time ...

  • Page 151

    ... FIGURE 15-10: PIC16F684 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. FIGURE 15-11: PIC16F684 A/D CONVERSION TIMING (SLEEP MODE) ...

  • Page 152

    ... PIC16F684 NOTES: DS41202D-page 150 © 2006 Microchip Technology Inc. ...

  • Page 153

    ... MHz 2 MHz 4 MHz © 2006 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC PIC16F684 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz DS41202D-page 151 DD ...

  • Page 154

    ... PIC16F684 FIGURE 16-2: MAXIMUM I DD 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 3.5 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz FIGURE 16-3: TYPICAL I DD 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst Case Temp (-40° ...

  • Page 155

    ... Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD Maximum IDD vs FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD PIC16F684 5.5V 5.0V 4.5V 20 MHz 4.5 5.0 5.5 DS41202D-page 153 ...

  • Page 156

    ... PIC16F684 FIGURE 16-6: MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 FIGURE 16-7: TYPICAL I DD 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 700 (-40° ...

  • Page 157

    ... Microchip Technology Inc. vs. V OVER F (EXTRC MODE) DD OSC EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ Maximum Typical 3.0 3.5 4.0 V (V) DD PIC16F684 4.5 5.0 5.5 4.5 5.0 5.5 DS41202D-page 155 ...

  • Page 158

    ... PIC16F684 FIGURE 16-10: I vs. V OVER Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125° 2.0 2.5 FIGURE 16-11: TYPICAL I DD 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 1,400 (-40°C to 125°C) 1,200 1,000 800 600 ...

  • Page 159

    ... Microchip Technology Inc. vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Typical (Sleep Mode all Peripherals Disabled) 3.0 3.5 4.0 V (V) DD PIC16F684 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz 4.5 5.0 5.5 DS41202D-page 157 ...

  • Page 160

    ... PIC16F684 FIGURE 16-14: MAXIMUM I PD 18.0 Typical: Statistical Mean @25°C Maximum: Mean + 3 16.0 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 FIGURE 16-15: COMPARATOR I 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp 140 (-40° ...

  • Page 161

    ... Microchip Technology Inc. OVER TEMPERATURE DD Maximum Typical 3.5 4.0 4.5 V (V) DD vs. V OVER TEMPERATURE PD DD Typical 3.0 3.5 4.0 V (V) DD PIC16F684 5.0 5.5 4.5 5.0 5.5 DS41202D-page 159 ...

  • Page 162

    ... PIC16F684 FIGURE 16-18: MAXIMUM WDT I 25.0 20.0 15.0 10.0 5.0 0.0 2.0 2.5 FIGURE 16-19: WDT PERIOD vs Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125° 2.0 2.5 DS41202D-page 160 vs. V OVER TEMPERATURE PD DD Maximum Max. 125°C Typical: Statistical Mean @25° ...

  • Page 163

    ... Microchip Technology Inc. (5.0V) DD Vdd = 5V Maximum Typical Minimum 25°C 85°C Temperature (°C) OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3.0 3.5 4.0 V (V) DD PIC16F684 125°C 4.5 5.0 5.5 DS41202D-page 161 ...

  • Page 164

    ... PIC16F684 FIGURE 16-22 vs. V REF PD 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 140 120 100 2.0 2.5 FIGURE 16-23: V vs. I OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst Case Temp (-40°C to 125°C) ...

  • Page 165

    ... Microchip Technology Inc. = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 I (mA 3.0V) DD -1.5 -2.0 -2.5 I (mA) OH PIC16F684 9.0 9.5 10.0 Max. -40°C Typ. 25°C Min. 125°C -3.0 -3.5 -4.0 DS41202D-page 163 ...

  • Page 166

    ... PIC16F684 FIGURE 16-26: V vs. I OVER TEMPERATURE ( 5.5 5.0 4.5 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst Case Temp (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 FIGURE 16-27: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst Case Temp (-40° ...

  • Page 167

    ... Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (32 kHz) DD Max. 125°C Max. 85°C Typ. 25°C 3.0 3.5 4.0 V (V) DD PIC16F684 OVER TEMPERATURE DD V Max. 125° Min. -40° Max. -40° Min. 125°C IL 4.5 5.0 5.5 4.5 5 ...

  • Page 168

    ... PIC16F684 FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 800 700 1.5V)/2 Note: 600 input = input = Transition from V 500 400 300 200 100 0 2.0 FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 700 1.5V)/2 600 Note: ...

  • Page 169

    ... Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125°C) 3.0 3.5 4.0 4.5 V (V) DD PIC16F684 4.5 5.0 5.5 5.0 5.5 DS41202D-page 167 ...

  • Page 170

    ... PIC16F684 FIGURE 16-34: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40° 2.0 2.5 3.0 FIGURE 16-35: MAXIMUM HFINTOSC START-UP TIMES vs 85°C 25°C 10 -40° 2.0 2.5 3.0 DS41202D-page 168 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40° ...

  • Page 171

    ... Microchip Technology Inc. OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp (-40°C to 125°C) 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD PIC16F684 4.5 5.0 5.5 (25°C) DD 4.5 5.0 5.5 DS41202D-page 169 ...

  • Page 172

    ... PIC16F684 FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41202D-page 170 3.0 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD (85°C) DD 4.5 5.0 5.5 (125°C) DD 4.5 5.0 5.5 © 2006 Microchip Technology Inc. ...

  • Page 173

    ... FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD PIC16F684 (-40°C) DD 5.0 5.5 DS41202D-page 171 ...

  • Page 174

    ... PIC16F684 NOTES: DS41202D-page 172 © 2006 Microchip Technology Inc. ...

  • Page 175

    ... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC16F684 Example PIC16F684-I/P 0510017 Example PIC16F684-E 0510017 Example ...

  • Page 176

    ... PIC16F684 17.2 Package Details The following sections give the technical details of the packages. 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...

  • Page 177

    ... L .016 .033 .050 .008 .009 .010 B .014 .017 .020 PIC16F684 A2 MILLIMETERS MIN NOM MAX 14 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 5.99 6.20 3.81 3.90 3.99 8.56 8.69 8.81 0.25 0.38 ...

  • Page 178

    ... PIC16F684 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...

  • Page 179

    ... E2 .090** – .110 D .152 .157 .163 D2 .090 – .110 b .010 .012 .014 L .012 .016 .020 K .008 – – PIC16F684 BOTTOM VIEW MILLIMETERS* MIN NOM MAX 16 0.65 BSC 0.80 0.90 1.00 0.00 0.02 0.05 0.20 REF 3.85 4.00 4.15 2.29** – ...

  • Page 180

    ... PIC16F684 NOTES: DS41202D-page 178 © 2006 Microchip Technology Inc. ...

  • Page 181

    ... Microchip Technology Inc. PIC16F684 APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC16F6XX Family of devices. B.1 PIC16F676 to PIC16F684 TABLE B-1: FEATURE COMPARISON Feature PIC16F676 Max Operating 20 MHz Speed Max Program 1024 ...

  • Page 182

    ... PIC16F684 NOTES: DS41202D-page 180 © 2006 Microchip Technology Inc. ...

  • Page 183

    ... Compare ..................................................................... 83 Crystal Operation ........................................................ 22 External RC Mode....................................................... 23 Fail-Safe Clock Monitor (FSCM) ................................. 29 In-Circuit Serial Programming Connections.............. 116 Interrupt Logic ........................................................... 109 MCLR Circuit............................................................. 102 On-Chip Reset Circuit ............................................... 101 PIC16F684.................................................................... 5 PWM (Enhanced)........................................................ 87 RA0 Pins ..................................................................... 35 RA1 Pins ..................................................................... 36 RA2 Pin....................................................................... 36 RA3 Pin....................................................................... 37 © 2006 Microchip Technology Inc. PIC16F684 RA4 Pin ...

  • Page 184

    ... PIC16F684 CMCON1 Register .............................................................. 63 Code Examples A/D Conversion ........................................................... 71 Assigning Prescaler to Timer0 .................................... 44 Assigning Prescaler to WDT ....................................... 44 Changing Between Capture Prescalers ...................... 82 Data EEPROM Read .................................................. 79 Data EEPROM Write .................................................. 79 Indirect Addressing ..................................................... 19 Initializing PORTA ....................................................... 31 Initializing PORTC....................................................... 40 Saving Status and W Registers in RAM ................... 111 Ultra Low-Power Wake-Up Initialization...................... 34 Write Verify ................................................................. 79 Code Protection ...

  • Page 185

    ... PCL and PCLATH............................................................... 19 Stack........................................................................... 19 PCON Register ........................................................... 18, 104 PICSTART Plus Development Programmer..................... 130 PIE1 Register ..................................................................... 16 Pin Diagram PDIP, SOIC, TSSOP .................................................... 2 QFN .............................................................................. 3 Pinout Descriptions PIC16F684 ................................................................... 6 PIR1 Register ..................................................................... 17 PORTA ............................................................................... 31 Additional Pin Functions ............................................. 32 ANSEL Register ................................................. 32 Interrupt-on-Change ........................................... 32 Ultra Low-Power Wake-Up ........................... 32, 34 Weak Pull-up ...................................................... 32 Associated registers ................................................... 39 Pin Descriptions and Diagrams .................................. 35 RA0 ...

  • Page 186

    ... PIC16F684 Map and Stack .............................................................. 7 Programming, Device Instructions .................................... 117 PWM Mode. See Enhanced Capture/Compare/PWM ........ 87 PWM1CON Register ........................................................... 98 R Reader Response ............................................................. 190 Read-Modify-Write Operations.......................................... 117 Registers ADCON0 (ADC Control 0) .......................................... 72 ADCON1 (ADC Control 1) .......................................... 72 ADRESH (ADC Result High) with ADFM = 0)............. 73 ADRESH (ADC Result High) with ADFM = 1)............. 73 ADRESL (ADC Result Low) with ADFM = 0) ...

  • Page 187

    ... REF EE W Wake-up Using Interrupts ................................................. 114 Watchdog Timer (WDT) .................................................... 112 Associated Registers ................................................ 113 Clock Source............................................................. 112 Modes ....................................................................... 112 Period........................................................................ 112 Specifications............................................................ 145 WDTCON Register ........................................................... 113 WPUA Register ................................................................... 33 WWW Address.................................................................. 189 WWW, On-Line Support ....................................................... 4 © 2006 Microchip Technology Inc. PIC16F684 DS41202D-page 185 ...

  • Page 188

    ... PIC16F684 NOTES: DS41202D-page 186 © 2006 Microchip Technology Inc. ...

  • Page 189

    ... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC16F684 should contact their distributor, DS41202D-page 187 ...

  • Page 190

    ... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F684 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...

  • Page 191

    ... Thin Shrink Small Outline (4.4 mm) SM Pattern: QTP, SQTP or ROM Code; Special Requirements (blank otherwise) © 2006 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F684-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC16F684-I/SO = Industrial Temp., SOIC package, 20 MHz (1) (Industrial) (Extended) Note 1: PIC16F684 . ...

  • Page 192

    ... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...