PIC16F74-I/P Microchip Technology Inc., PIC16F74-I/P Datasheet - Page 58

• Manufacturer Part Number: PIC16F74-I/P
• Description: 40 PIN, 7 KB FLASH, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F74-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
8.4.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
8.4.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.4.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
TABLE 8-3:
DS30325B-page 56
Address
0Bh,8Bh,
10Bh,18Bh
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
Legend:
Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
Note:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
INTCON
PIR1
PIR2
PIE1
PIE2
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
Name
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
PORTC Data Direction Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
PSPIF
PSPIE
Bit 7
GIE
—
—
—
—
—
(1)
(1)
Bit 6
PEIE
ADIF
ADIE
—
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR0IE
CCP1X
CCP2X
RCIE
Bit 5
RCIF
—
—
CCP1Y
CCP2Y
Bit 4
INTE
TXIF
TXIE
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
SSPIF
SSPIE
Bit 3
RBIE
—
—
8.4.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note:
TMR0IF
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Bit 2
—
—
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
SPECIAL EVENT TRIGGER
TMR2IF TMR1IF 0000 0000 0000 0000
Bit 1
INTF
—
—
CCP2IE ---- ---0 ---- ---0
CCP2IF ---- ---0 ---- ---0
 2002 Microchip Technology Inc.
Bit 0
RBIF
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on:
POR,
BOR
Value on
RESETS
all other