PIC16F74-I/P Microchip Technology Inc., PIC16F74-I/P Datasheet - Page 64

• Manufacturer Part Number: PIC16F74-I/P
• Description: 40 PIN, 7 KB FLASH, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F74-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
FIGURE 9-1:
DS30325B-page 62
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SCL
Peripheral OE
Read
SS Control
Select
TRISC<3>
Edge
bit0
Enable
Select
Edge
SSPBUF reg
SSP BLOCK DIAGRAM
(SPI MODE)
SSPM3:SSPM0
SSPSR reg
Clock Select
4
2
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
T
CY
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
.
cleared
be configured such that RA5 is a digital I/O
Note 1: When the SPI is in Slave mode with SS pin
2: If the SPI is used in Slave mode with
3: When the SPI is in Slave mode with SS
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to V
CKE = '1', then the SS pin control must be
enabled.
pin control enabled (SSPCON<3:0> =
‘0100’), the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC controls the
state that is read back from the
TRISC<5> bit (see Section 4.3 for infor-
mation on PORTC). If Read-Modify-Write
instructions, such as BSF are performed
on the TRISC register while the SS pin is
high, this will cause the TRISC<5> bit to
be set, thus disabling the SDO output.
DD
.
 2002 Microchip Technology Inc.