PIC16F74-I/P Microchip Technology Inc., PIC16F74-I/P Datasheet - Page 96

• Manufacturer Part Number: PIC16F74-I/P
• Description: 40 PIN, 7 KB FLASH, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F74-I/P

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
12.4
PIC16F7X devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 12-5, is suggested.
FIGURE 12-5:
12.5
A Power-on Reset pulse is generated on-chip when
V
take advantage of the POR, tie the MCLR pin to V
described in Section 12.4. A maximum rise time for
V
details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. For additional information, refer to Application
Note,
(DS00607).
DS30325B-page 94
DD
DD
rise is detected (in the range of 1.2V - 1.7V). To
is specified. See the Electrical Specifications for
V
DD
AN607,
MCLR
Power-on Reset (POR)
R1
1 k Ω (or greater)
C1
0.1 µ F
(optional, not critical)
“Power-up
RECOMMENDED MCLR
CIRCUIT
DD
Trouble
. The use of an RC
MCLR
PIC16F7X
Shooting”
DD
as
12.6
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows V
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip to chip, due
to V
parameters for details (T
12.7
The Oscillator Start-up Timer (OST) provides 1024 oscil-
lator cycles (from OSC1 input) delay after the PWRT
delay is over (if enabled). This helps to ensure that the
crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.
12.8
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If V
(parameter D005, about 4V) for longer than T
(parameter #35, about 100 µS), the brown-out situation
will reset the device. If V
than T
Once the brown-out occurs, the device will remain in
Brown-out Reset until V
Power-up Timer then keeps the device in RESET for
T
below V
cess will restart when V
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
12.9
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F7X device operating in parallel.
Table 12-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 12-6
shows the RESET conditions for all the registers.
PWRT
DD
BOR
, temperature and process variation. See DC
(parameter #33, about 72 mS). If V
BOR
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Time-out Sequence
, a RESET may not occur.
during T
PWRT
 2002 Microchip Technology Inc.
DD
PWRT
DD
DD
, the Brown-out Reset pro-
rises above V
falls below V
rises above V
, parameter #33).
DD
DD
to rise to an accept-
falls below V
DD
BOR
BOR
should fall
BOR
, with the
for less
. The
BOR
BOR