PIC10F200-I/P Microchip Technology Inc., PIC10F200-I/P Datasheet - Page 56

• Manufacturer Part Number: PIC10F200-I/P
• Description: 8 PIN, 384 B FLASH, 16 RAM, 4 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC10F200-I/P

• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 4 MHz
• Input Output: 4
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 375 Bytes
• Ram Size: 16 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC10F200/202/204/206
BTFSS
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CALL
Syntax:
Operands:
Operation:
Status Affected: None
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
DS41239C-page 54
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0
0
skip if (f<b>) = 1
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
Subroutine Call
[ label ] CALL k
0
(PC) + 1
k
(STATUS<6:5>)
0
Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
Clear f
[ label ] CLRF
0
00h
1
The contents of register ‘f’ are
cleared and the Z bit is set.
f
b < 7
k
f
PC<7:0>;
PC<8>
Z
31
31
255
(f);
Top-of-Stack;
f
PC<10:9>;
Preliminary
CLRW
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected: TO, PD
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected: Z
Description:
Clear W
[ label ] CLRW
None
00h
1
The W register is cleared. Zero bit
(Z) is set.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h
0
1
1
The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
Complement f
[ label ] COMF
0
d
(f)
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
f
[0,1]
Z
WDT prescaler (if assigned);
TO;
PD
(dest)
© 2006 Microchip Technology Inc.
31
(W);
WDT;
f,d