PIC16F1826-E/P Microchip Technology Inc., PIC16F1826-E/P Datasheet - Page 281

• Manufacturer Part Number: PIC16F1826-E/P
• Description: 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V

REGISTER 25-3:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0/0
GCEN
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
GCEN: General Call Enable bit (in I
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (in I
1 = Acknowledge was not received
0 = Acknowledge was received
ACKDT: Acknowledge Data bit (in I
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (in I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (in I
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit (in I
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (in I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
ACKSTAT
R-0/0
Automatically cleared by hardware.
SSPxCON2: SSPx CONTROL REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
ACKDT
R/S/HS-0/0
2
ACKEN
2
C Master mode only)
C
2
2
2
C mode only)
C Slave mode only)
C Master mode only)
2
C Master mode only)
2
C mode only)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware
R/S/HS-0/0
2
RCEN
C module is not in the Idle mode, this bit may not be
2
2
C Master mode only)
C Master mode only)
PIC16(L)F1826/27
R/S/HS-0/0
PEN
S = User set
R/S/HS-0/0
RSEN
DS41391D-page 281
R/W/HS-0/0
SEN
bit 0