PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 167

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.2.14
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to ‘0’. When the baud rate generator times
out, the SCL pin will be brought high and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set (Figure 15-31).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
FIGURE 15-31:
BRG
2000 Microchip Technology Inc.
later, the PEN bit is cleared and the SSPIF bit is
STOP CONDITION TIMING
SCL
SDA
Write to SSPCON2
Falling Edge of
9th Clock
Note: T
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup STOP condition.
T
T
BRG
BRG
BRG
T
SCL brought high after T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
P
T
BRG
15.2.14.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set.
, followed by SDA = 1 for T
BRG
.
WCOL Status Flag
PIC17C7XX
BRG
DS30289B-page 167