PIC16F676-I/ST Microchip Technology Inc., PIC16F676-I/ST Datasheet - Page 22

• Manufacturer Part Number: PIC16F676-I/ST
• Description: 14 PIN, 1.75 KB FLASH, 64 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F676-I/ST

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin TSSO
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F630/676
REGISTER 3-2:
REGISTER 3-3:
3.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR'd together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
DS40039C-page 20
bit 7-6:
bit 5-0:
bit 7-6
bit 5-4
bit 3
bit 2-0
INTERRUPT-ON-CHANGE
TRISA — PORTA TRISTATE REGISTER (ADDRESS: 85h)
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
Unimplemented: Read as ’0’
TRISA<5:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
bit 7
Legend:
R = Readable bit
- n = Value at POR
Legend:
R = Readable bit
- n = Value at POR
Note:
U-0
U-0
—
—
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
TRISA<3> always reads 1.
U-0
U-0
—
—
TRISA5
WPUA5
R/W-x
R/W-1
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
TRISA4
WPUA4
R/W-x
R/W-1
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
Note:
Any read or write of PORTA. This will end the
mismatch condition.
Clear the flag bit RAIF.
TRISA3
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
—
R-1
WPUA2
R/W-1
TRISA2
R/W-x
 2003 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
R/W-1
TRISA1
R/W-x
WPUA0
TRISA0
R/W-1
R/W-x
bit 0
bit 0