24LC512-E/SM Microchip Technology Inc., 24LC512-E/SM Datasheet - Page 10

• Manufacturer Part Number: 24LC512-E/SM
• Description: 512K, 64K X 8, 2.5V SER EE, EXT, SOIC-8
• Manufacturer: Microchip Technology Inc.

Specifications of 24LC512-E/SM

• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24AA512/24LC512/24FC512
6.0
6.1
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX512. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX512, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX512 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX512 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
The write control byte, word address and the first data
byte are transmitted to the 24XX512 in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 127 additional
bytes, which are temporarily stored in the on-chip page
buffer and will be written into memory after the master
has transmitted a Stop condition. After receipt of each
word, the seven lower Address Pointer bits are inter-
nally incremented by one. If the master should transmit
more than 128 bytes prior to generating the Stop con-
dition, the address counter will roll over and the previ-
ously received data will be overwritten. As with the byte
write operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
DS21754J-page 10
WRITE OPERATIONS
Byte Write
Page Write
6.3
The WP pin allows the user to write-protect the entire
array (0000-FFFF) when the pin is tied to V
V
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
SS
Note:
the write protection is disabled. The WP pin is
Write Protection
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
© 2008 Microchip Technology Inc.
CC
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