24LC512-E/SM Microchip Technology Inc., 24LC512-E/SM Datasheet - Page 7

• Manufacturer Part Number: 24LC512-E/SM
• Description: 512K, 64K X 8, 2.5V SER EE, EXT, SOIC-8
• Manufacturer: Microchip Technology Inc.

Specifications of 24LC512-E/SM

• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Both data and clock lines remain high.
4.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
© 2008 Microchip Technology Inc.
is not busy.
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
BUS CHARACTERISTICS
Bus Not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
Data Valid (D)
24AA512/24LC512/24FC512
4.5
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit. See Figure 4-2 for acknowledge timing.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX512) will leave the data line high to enable
the master to generate the Stop condition.
Note:
Acknowledge
The 24XX512 does not generate any
Acknowledge bits if an internal programming
cycle is in progress.
DS21754J-page 7