PIC18LF24K22-I/ML Microchip Technology Inc., PIC18LF24K22-I/ML Datasheet - Page 102

• Manufacturer Part Number: PIC18LF24K22-I/ML
• Description: 16KB, FLASH, 768BYTES-RAM, 8-BIT FAMILY, NANOWATT XLP, 28 QFN 6X6MM TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18LF24K22-I/ML

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 48 MHz
• Temperature Range: –40 to 125 °C
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18(L)F2X/4XK22
EXAMPLE 6-3:
DS41412D-page 102
READ_BLOCK
MODIFY_WORD
ERASE_BLOCK
Required
Sequence
WRITE_BUFFER_BACK
WRITE_BYTE_TO_HREGS
WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLRD*+
MOVF
MOVWF
DECFSZ
BRA
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
TBLRD*-
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVF
MOVWF
TBLWT+*
D'64’
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TABLAT, W
POSTINC0
COUNTER
READ_BLOCK
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
BlockSize
COUNTER
D’64’/BlockSize
COUNTER2
POSTINC0, W
TABLAT
Preliminary
; number of bytes in erase block
; point to buffer
; Load TBLPTR with the base
; address of the memory block
; read into TABLAT, and inc
; get data
; store data
; done?
; repeat
; point to buffer
; update buffer word
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
; dummy read decrement
; point to buffer
; number of bytes in holding register
; number of write blocks in 64 bytes
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
 2010 Microchip Technology Inc.