PIC18LF24K22-I/ML Microchip Technology Inc., PIC18LF24K22-I/ML Datasheet - Page 169

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PIC18LF24K22-I/ML

Manufacturer Part Number
PIC18LF24K22-I/ML
Description
16KB, FLASH, 768BYTES-RAM, 8-BIT FAMILY, NANOWATT XLP, 28 QFN 6X6MM TUBE
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18LF24K22-I/ML

A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
48 MHz
Temperature Range
–40 to 125 °C
Timers
1-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
FIGURE 12-7:
12.12 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power con-
sumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5
(TMR5MD) are in the PMD0 Register. See
“Power-Managed Modes”
 2010 Microchip Technology Inc.
TIMER1/3/5
TMRxGIF
TMRxGE
TxGSPM
TxGPOL
TxGVAL
TxGGO/
TxG_IN
TxGTM
DONE
TxCKI
TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
Cleared by software
N
for more information.
Counting enabled on
rising edge of TxG
Set by software
Section 3.0
Preliminary
N + 1
falling edge of TxGVAL
Set by hardware on
N + 2
PIC18(L)F2X/4XK22
N + 3
N + 4
Cleared by hardware on
falling edge of TxGVAL
DS41412D-page 169
Cleared by
software

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