PIC18LF24K22-I/ML Microchip Technology Inc., PIC18LF24K22-I/ML Datasheet - Page 273

• Manufacturer Part Number: PIC18LF24K22-I/ML
• Description: 16KB, FLASH, 768BYTES-RAM, 8-BIT FAMILY, NANOWATT XLP, 28 QFN 6X6MM TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18LF24K22-I/ML

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin QFN
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 48 MHz
• Temperature Range: –40 to 125 °C
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 16-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
SPEN
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0 = Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREGx register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
R/W-0
RX9
RCSTAX: RECEIVE STATUS AND CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
SREN
R/W-0
CREN
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADDEN
R/W-0
PIC18(L)F2X/4XK22
FERR
R-0
x = Bit is unknown
OERR
R-0
DS41412D-page 273
RX9D
R-0
bit 0