ISP1506BBS-T ST-Ericsson Inc, ISP1506BBS-T Datasheet - Page 34

• Manufacturer Part Number: ISP1506BBS-T
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
ISP1506A_ISP1506B_1
Product data sheet
Fig 14. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[3:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the
ISP1506 operates just as in full-speed mode, and sends all data with the full-speed rise
and fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1506
will automatically send a preamble header at full-speed bit rate before sending the link
packet at low-speed bit rate. The ISP1506 will ensure a minimum gap of four full-speed bit
times between the last bit of the full-speed PRE PID and the first bit of the low-speed
packet SYNC. The ISP1506 will drive a J for at least one full-speed bit time after sending
the PRE PID, after which the pull-up resistor can hold the J state on the bus. An example
transmit packet is shown in
In preamble mode, the ISP1506 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
N 1
RX end delay
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 01 — 30 May 2007
Figure
link decision time (1 to 14 clocks)
15.
IDLE
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2007. All rights reserved.
SYNC
D0
004aaa892
34 of 79
D1