ISP1506BBS-T ST-Ericsson Inc, ISP1506BBS-T Datasheet - Page 51

• Manufacturer Part Number: ISP1506BBS-T
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 38.
Table 39.
Table 40.
Table 41.
ISP1506A_ISP1506B_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH[7:0]
Debug register (address R = 15h) bit allocation
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
10.1.10 Scratch register
10.1.11 Reserved
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 Power Control register
10.1.9 Debug register
R/W/S/C
Symbol
-
LINESTATE1
LINESTATE0
R
7
0
7
0
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
Table 40
purposes.
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Address 30h to 3Fh contains vendor-specific registers.
This register controls various aspects of the ISP1506.
the register.
Access
R/W/S/C
R/W/S/C
R
6
0
6
0
shows the bit description of the Scratch register. It is an empty register for testing
reserved
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
Value
00h
R/W/S/C
R
5
0
5
0
reserved
Rev. 01 — 30 May 2007
Description
Scratch: This is an empty register byte for testing purposes.
Software can read, write, set and clear this register, and the
functionality of the PHY will not be affected.
R/W/S/C
R
4
0
4
0
BVALID_
R/W/S/C
FALL
R
3
0
3
0
ISP1506A; ISP1506B
Table
Table 41
BVALID_
R/W/S/C
RISE
38. This register indicates the
ULPI HS USB OTG transceiver
R
2
0
2
0
shows the bit allocation of
reserved
R/W/S/C
STATE1
LINE
R
1
0
1
0
© NXP B.V. 2007. All rights reserved.
IGNORE_
R/W/S/C
STATE0
RESET
LINE
R
0
0
0
0
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