ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet
ICS1893Y-10LF
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800-1935-5
ICS1893Y-10LF
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ICS1893Y-10LF Summary of contents
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... The ICS1893Y- low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893Y-10 architecture is based on the ICS1892. The ICS1893Y-10 supports managed or unmanaged node, repeater, and switch applications. The ICS1893Y-10 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer ...
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... ICS1893Y-10 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 13 Chapter 2 Conventions and Nomenclature..................................................................................... 15 Chapter 3 Overview of the ICS1893Y-10 .......................................................................................... 17 3.1 100Base-TX Operation ..........................................................................................18 3.2 10Base-T Operation ...............................................................................................18 Chapter 4 Operating Modes Overview............................................................................................. 19 4.1 Reset Operations ...................................................................................................20 4.1.1 General Reset Operations .....................................................................................20 4.1.2 Specific Reset Operations .....................................................................................21 4.2 Power-Down Operations ...
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... Operation: Auto Polarity Correction .......................................................57 6.5.14 10Base-T Operation: Isolation Transformer ...........................................................57 6.6 Functional Block: Management Interface ...............................................................58 6.6.1 Management Register Set Summary .....................................................................58 6.6.2 Management Frame Structure ...............................................................................58 ICS1893Y-10 Rev F 1/20/04 Table of Contents Title Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 3 Table of Contents Page January, 2004 ...
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... ICS1893Y-10 Data Sheet - Release Section Chapter 7 Management Register Set ............................................................................................... 61 7.1 Introduction to Management Register Set .............................................................62 7.1.1 Management Register Set Outline .........................................................................62 7.1.2 Management Register Bit Access ..........................................................................63 7.1.3 Management Register Bit Default Values ..............................................................63 7.1.4 Management Register Bit Special Functions .........................................................64 7.2 Register 0: Control Register ...................................................................................65 7.2.1 Reset (bit 0 ...
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... IEEE Reserved Bit (bit 8.14) ..................................................................................88 7.10.3 Message Page (bit 8.13) ........................................................................................88 7.10.4 Acknowledge 2 (bit 8.12) .......................................................................................88 7.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0) .................................88 ICS1893Y-10 Rev F 1/20/04 Table of Contents Title Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 5 Table of Contents ...
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... ICS1893Y-10 Data Sheet - Release Section 7.11 Register 16: Extended Control Register ................................................................89 7.11.1 Command Override Write Enable (bit 16.15) .........................................................90 7.11.2 ICS Reserved (bits 16.14:11) .................................................................................90 7.11.3 PHY Address (bits 16.10:6) ...................................................................................90 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) .....................................................90 7.11.5 ICS Reserved (bit 16.4) .........................................................................................90 7.11.6 NRZ/NRZI Encoding (bit 16 ...
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... MII / 100M Stream Interface: Synchronous Receive Timing ................................130 9.5.7 MII Management Interface Timing .......................................................................131 9.5.8 10M Serial Interface: Receive Latency ................................................................132 9.5.9 10M Media Independent Interface: Receive Latency ...........................................133 ICS1893Y-10 Rev F 1/20/04 Table of Contents Title Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 7 Table of Contents ...
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... Jabber Timing .....................................................................................144 9.5.21 10Base-T: Normal Link Pulse Timing ..................................................................145 9.5.22 Auto-Negotiation Fast Link Pulse Timing .............................................................146 Chapter 10 Physical Dimensions of ICS1893Y-10 Package ........................................................ 147 Chapter 11 Ordering Information..................................................................................................... 149 ICS1893Y-10 Rev F 1/20/04 Table of Contents Title Copyright © 2004, Integrated Circuit Systems, Inc. ...
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... Changes to table values. – Chapter 10, “Physical Dimensions of ICS1893Y-10 ICS1893Y-10 Rev F 1/20/04 ICS1893Y-10”. Change to text in 1(a). Scrambler/Descrambler”. Added paragraph. 4.12:10)”. New paragraph. (Subsequent paragraphs reflect Descriptions”. ICS1893Y-10 pin names have changes. Current”. Changes to text and table reflect Package” ...
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... Section 5.5.1, “Twisted-Pair Transmitter Interface” Interface” are two new sections with two new figures. – Section 6.6, “Clock Reference Interface” ICS1893Y-10 does not work with a crystal. (Section 6.6.1 and Section 6.6.2 are deleted.) – Section 5.8, “Status Interface” – A new figure, Figure – ...
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... Section 7.14.6, “ICS Reserved (bits – Section 8.14.7, “Force LEDs On (bit 19.5)”, – Section 8.14.8, “ICS Reserved (bits 19.4:1)”, – Section 9,1, “ICS1893Y-10 Pin Diagram”, – Table 8-1, changed pin 20 from N/C to REG. – Table 8-3, revised P3TD Pin 62 Description. ...
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... ICS1893Y-10 Data Sheet - Release • This release of this document, Rev F, is dated 20 January 2004. The following list indicates where changes occur. – Table of Contents reflect page renumbering. – Table 8-18 to correct Bit 17.3 definition – Figure 12.1 to add Lead-Free – Section 5.6, add Crystal Operation ICS1893Y-10 Rev F 1/20/04 Copyright © ...
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... Not Applicable NLP Normal Link Pulse No. Number NRZ Not Return to Zero NRZI Not Return to Zero, Invert on one OSI Open Systems Interconnection ICS1893Y-10 Rev F 1/20/04 Interpretation Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 13 Chapter 1 Abbreviations and Acronyms January, 2004 ...
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... Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893Y- physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ppm ...
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... All pin or signal names are provided in capital letters. • A pin name that includes a forward slash ‘/’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893Y-10 functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... The terms ‘cleared’, ‘inactive’, and ‘de-asserted’ are synonymous. They do not necessarily infer logic zero. In reference to the ICS1893Y-10, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893Y-10, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © ...
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... Auto-Negotiation sublayer The ICS1893Y-10 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893Y-10 can interface directly to the MAC and offers multiple, configurable modes of operation. Alternately, this configurable interface can be connected to a repeater, which extends the physical layer of the OSI model ...
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... Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893Y-10 encapsulates each MAC/repeater frame, including the preamble, with an SSD and an ESD. As per the ISO/IEC Standard, the ICS1893Y-10 replaces the first octet of each MAC preamble with an SSD and appends an ESD to the end of each MAC/repeater frame. ...
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... ICS1893Y- use, either its hardware pins or its register bits. When the HW/SW bit is logic zero the ICS1893Y- hardware mode. In hardware mode, the hardware pins have priority over the internal registers for establishing the configuration settings of the ICS1893Y-10 ...
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... Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed 4.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893Y-10 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893Y-10 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.) ICS1893Y-10 Rev F 1/20/04 Operations” ...
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... Section 4.1.1.1, “Entering Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893Y-10 completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in first five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893Y-10 sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... For example, if the ICS1893Y-10 supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode ...
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... Data conversion from both parallel-to-serial and serial-to-parallel formats • Manchester data encoding/decoding • Data transmission/reception over a twisted-pair medium In addition, in 10Base-T mode, the ICS1893Y-10 provides a variety of control and status means to assist with Link Segment management. For more information on 10Base-T, see 10Base-T Operations”. 4.7 Half-Duplex and Full-Duplex Operations The ICS1893Y-10 supports half-duplex and full-duplex operations for both 10Base-T and 100Base-TX applications ...
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... ICS1893Y-10 - Release Chapter 5 Interface Overviews The ICS1893Y-10 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “100M Symbol Interface” • ...
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... PHY and the MAC/repeater as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. The ICS1893Y-10 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles). ...
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... In the 100M Symbol Interface mode, the ICS1893Y-10 continues to assert the CRS signal using its PCS logic. This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received from the PMA sublayer serially ...
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... ICS1893Y-10 Data Sheet - Release Table 5-1 lists the pin mappings for the ICS1893Y-10 100M Symbol Interface mode. Table 5-1. Pin Mappings for 100M Symbol Interface Mode Default 10M / 100M MII Pin Names COL No connect. [Because the MAC/repeater sources both active and ‘idle’ data, a PHY cannot distinguish between an active and idle transmission channel (that is PHY the transmit channel always appears active) ...
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... ICS1893Y-10 - Release 5.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893Y-10 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ideally suited to applications that already incorporate a serial 10Base-T MAC with a standard ‘ ...
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... ICS1893Y-10 Data Sheet - Release Table 5-2 lists the pin mappings for the ICS1893Y-10 10M Serial Interface mode. Table 5-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC MDIO MDIO RXCLK ...
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... ICS1893Y-10. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893Y-10. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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... ICS1893Y-10 twisted-pair transmitter interface. Two 61.9 Ω 1% resistors are in series, with a 120-nH 5% inductor between them. These components • form a network that connects across both the transformer and the ICS1893Y-10 TP_TXP and TP_TXN pins. • The ICS1893Y-10 supplies the power to the transformer. (No VDD connection is required.) • ...
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... No bypass capacitor is used with the receive transformer center tap. • A 4.7-pF capacitor must be included across the ICS1893Y-10 side of the receive transformer. Note: 1. Keep leads as short as possible. 2. Install the resistor network as close to the ICS1893Y-10 as possible. Figure 5-2. ICS1893Y-10 Receiver Twisted Pair TP_RXP 13 4 ...
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... MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893Y-10 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 5 ...
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... If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893Y-10. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the bypass caps serve to adjust the final frequency of the crystal oscillation ...
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... Functionally, the RXTRI pin affects the MII receive channel in the same way as the Control Register’s isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.) The ICS1893Y-10 can tri-state these seven signals for all five types of MAC/Repeater Interface configurations, not just the MII interface. ...
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... ICS1893Y-10 - Release 5.8 Status Interface The ICS1893Y-10 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status. In addition, as listed in that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table Table 5-5 ...
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... ICS1893Y-10 Data Sheet - Release Figure 5-4 shows typical biasing and LED connections for the ICS1893Y-10. Figure 5-4. ICS1893Y-10 LED - PHY Address P4RD P3TD 64 62 REC TRANS 10K Ω 10K Ω This circuit decodes to PHY address = 1. Note: 1. All LED pins must be set during reset. ...
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... ICS1893Y-10 - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893Y-10 functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” • ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893Y-10). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... ICS1893Y-10 has the auto-negotiation process enabled and it is operating with a 10Base-T remote link partner, the ICS1893Y-10 monitors the link and automatically selects the 10Base-T operating mode – even though the remote link partner does not support auto-negotiation. This process, called parallel detection, is automatic and transparent to the remote link partner and allows the ICS1893Y-10 to function seamlessly with existing legacy network structures without any management intervention ...
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... The ICS1893Y-10 obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893Y-10 and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893Y-10 transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893Y-10 reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel. ...
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... Monitor”. After the Auto-Negotiation Arbitration State Machine reaches its final state (which is Auto-Negotiation Complete), only an STA read of the QuickPoll Detailed Status Register or an ICS1893Y-10 reset can alter these status bits. Any of the following situations initiates a restart of the ICS1893Y-10 Auto-Negotiation sublayer: • ...
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... STA can determine the cause of the link failure by using the outputs of the ICS1893Y-10 Auto-Negotiation Progress Monitor. The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the history and the present state of the auto-negotiation process ...
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... Note: When configured for 100M Symbol mode operations, the MAC/Repeater Interface bypasses most of the PCS. When the ICS1893Y-10 MAC/Repeater Interface is in this mode, most of its PCS Transmit and Receive modules are inactive. However, its PCS control functions (CRS and COL) remain operational. ...
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... Full-duplex mode, COL is always FALSE. 6.3.3.2 PMA Transmit Module The ICS1893Y-10 PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. ...
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... Both the PCS and PMA sublayers have Receive modules. 6.3.4.1 PCS Receive Module The ICS1893Y-10 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893Y-10 to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see ...
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... Baseline wander adversely affects the noise immunity of the receiver, because the ‘baseline’ signal moves or ‘wanders’ from its nominal DC value. The ICS1893Y-10 uses a unique technique to restore the DC component ‘lost’ by the medium result, the design is very robust, immune to noise and independent of the data stream ...
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... The DSP-based adaptive equalizer uses a technique that compensates for a wide range of cable lengths. The optimizing parameter for the equalization process is the overall bit error rate of the ICS1893Y-10. This technique closes the loop on the entire data reception process and provides a very high overall reliability. ...
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... ICS1893Y-10 Data Sheet - Release 6.4.7 100Base-TX Operation: Auto Polarity Correction The ICS1893Y-10 can sense and then automatically correct a signal polarity that is reversed on its Twisted-Pair Receiver inputs. A signal polarity reversal occurs when the input signals on the TP_RXP and TP_RXN pins are crossed or swapped (a problem that can occur during network installation or wiring). This function is primarily a 10Base-T function, however also active during Auto-Negotiation ...
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... Operation: Manchester Encoder/Decoder During data transmission the ICS1893Y-10 acquires data from its MAC/Repeater Interface in either 4-bit nibbles serial bit stream. The ICS1893Y-10 converts this data into a Manchester-encoded signal for presentation to its MDI, as required by the ISO/IEC specification Manchester-encoded signal, all logic: • ...
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... MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the ICS1893Y-10 periodically transmits link pulses at a rate of one link pulse every compliance with the ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1893Y-10 continues transmitting link pulses even while receiving data ...
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... The ICS1893Y-10 has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state machines. These functions indicate whether the ICS1893Y-10 is (1) transmitting data, (2) receiving data collision state (that is, the ICS1893Y-10 is both transmitting and receiving data on its twisted-pair medium, as defined in the ISO/IEC 8802-3 standard). When the ICS1893Y-10 is configured for: • ...
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... Twisted-Pair Transmitter. During this time, when interrupting the data stream and asserting its COL signal, the ICS1893Y-10 transmits Normal Link Pulses and sets its QuickPoll Detailed Status Register’s Jabber Detected bit (bit 17.2) to logic one. This bit is a latching high (LH) bit. (For more information on latching high and latching low bits, see Bits” ...
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... Normal Link Pulses (NLPs). In 10Base-T mode, an ICS1893Y-10 transmits and receives NLPs when its link is in the Idle state. In 100Base-TX mode, an ICS1893Y-10 transmits and receives NLPs during Auto-Negotiation. An STA can control this feature using the 10Base-T Operations Register bit 18.3, the Auto Polarity-Inhibit bit. When this bit is logic: • ...
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... Management Frame Structure The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893Y-10, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893Y-10 does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... Read, (OP is 10b) the ICS1893Y-10 obtains the contents of the register identified in the REGAD field and returns this Data to the STA synchronously with its MDC signal. • Write, (OP is 01b) the ICS1893Y-10 stores the value of the Data field in the register identified in the REGAD field. If the STA attempts to: • ...
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... Section 7.12, “Register 17: Quick Poll Detailed Status Register” • Section 7.13, “Register 18: 10Base-T Operations Register” • Section 7.14, “Register 19: Extended Control Register 2” ICS1893Y-10 Rev F 1/20/04 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 61 Chapter 7 Management Register Set ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (ICS) Registers Table 7-2 lists the ICS-specific registers that the ICS1893Y-10 implements. These registers enhance the performance of the ICS1893Y-10 and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. ICS-Specific Registers Register Address 16 ...
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... Read/Write Zero R/W0 7.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893Y-10 sets all Management Register bits to their default values after a reset. ICS1893Y-10 Management Register bits. Table 7-4. Range of Possible Valid Default Values for ICS1893Y-10 Register Bits Default Condition – ...
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... STA access. The SC bits have a default value of logic zero and are triggers to begin execution of a function. When the STA writes a logic one bit, the ICS1893Y-10 begins executing the function assigned to that bit. After the ICS1893Y-10 completes executing the function, it clears the bit to indicate that the action is complete ...
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... Reserved bits. 7.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893Y-10 software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... Auto-Negotiation sublayer. When bit 0.12 is logic: – Zero: • The ICS1893Y-10 disables the Auto-Negotiation sublayer. • The ICS1893Y-10 bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data rate and the duplex mode. – One: • ...
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... Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893Y-10 isolates itself from the MAC/Repeater Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893Y-10 does not isolate its MAC/Repeater Interface. 7.2.7 Restart Auto-Negotiation (bit 0.9) This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is logic one) ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893Y-10 is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893Y-10 isolates bit 0.8 and uses the DPXSEL input pin to establish the Duplex mode for the ICS1893Y-10. In this Hardware mode: – Bit 0.8 is undefined. ...
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... As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. 7.3.1 100Base-T4 (bit 1.15) The STA reads this bit to learn if the ICS1893Y-10 can support 100Base-T4 operations. Bit 1.15 of the ICS1893Y-10 is permanently set to logic zero, which informs an STA that the ICS1893Y-10 cannot support 100Base-T4 operations. ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893Y-10 supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893Y-10 Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893Y-10 implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893Y-10 ...
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... ICS1893Y-10 Data Sheet - Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893Y-10 sets bit 1.4 based on the Remote Fault bit received from its remote link partner. The ICS1893Y-10 receives the Remote Fault bit as part of the Link Code Word exchanged during the auto-negotiation process ...
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... Operation: Link 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893Y-10 detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893Y-10 Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893Y-10 Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... ICS1893Y-10 Data Sheet - Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • ...
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... The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from least significant to most significant, and from left to right. of the OUI (in IEEE Std 802-1990 format) to Management Registers 2 and 3. Table 7-8. IEEE-Assigned Organizationally Unique Identifier First Octet 2.15:12 ICS1893Y-10 Rev F 1/20/04 Table 7-8 Second Octet ...
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... The most-significant 6 bits of register 3 (that is, bits 3.15:10) include OUI bits 19 through 24. OUI bit 19 is stored in bit 3.15, while OUI bit 24 is stored in bit 3.10. 7.5.2 Manufacturer’s Model Number (bits 3.9:4) The model number for the ICS1893Y- (decimal stored in bit 3.9:4 as 00100b. ICS1893Y-10 Rev F 1/20/04 Section 7.4, “Register 2: PHY Identifier ...
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... ICS1893Y-10 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs when the ICS1893Y-10 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register. ...
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... Link Code Word that the ICS1893Y-10 exchanges with its remote link partner. The ICS1893Y-10 sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893Y-10 does not detect a link fault, it clears bit 4.13 to logic zero. ...
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... ICS1893Y-10 advertises. The ICS1893Y-10 updates the Auto-Negotiation Advertisement Register TAF field to indicate the selection made by these pins. The ICS1893Y-10 sets only one of these four bits to logic one. The other three bits are a logic zero. Note: The ICS1893Y-10 does not alter the value of the Status Register bits ...
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... ICS1893Y-10 to provide these technologies. Note: 1. The ICS1893Y-10 does not alter the value of the Status Register bits based on the TAF bits in register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the capabilities of the ICS1893Y-10 ...
Page 81
... During the auto-negotiation process, the ICS1893Y-10 advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
Page 82
... Zero, it indicates that the remote link partner has not received the ICS1893Y-10 Link Control Word. • One, it indicates to the ICS1893Y-10 / STA that the remote link partner has acknowledged reception of the ICS1893Y-10 Link Control Word. 7.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893Y-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations ...
Page 84
... Next Page bit in its Link Control Word. 7.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893Y-10 to support the Next Page features of the auto-negotiation process. The ICS1893Y-10 sets this bit to a logic one to indicate that it can support these features ...
Page 85
... Message code field /Unformatted code field † As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. ICS1893Y-10 Rev F 1/20/04 Table 7-14, see Chapter 1, “Abbreviations and When Bit = 0 ...
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... Zero, it indicates that the ICS1893Y-10 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893Y-10 can comply with the message. 7.9.5 Toggle (bit 7.11) The Toggle (T) bit (bit 7.11) is used to synchronize the transmission of Next Page messages with the remote link partner ...
Page 87
... Message code field /Unformatted code field † As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. ICS1893Y-10 Rev F 1/20/04 Table 7-15, see Chapter 1, “Abbreviations and When Bit = 0 ...
Page 88
... Zero, it indicates that the ICS1893Y-10 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893Y-10 can comply with the message. If the previous Next Page Link Control Word Toggle bit has a value of logic: • Zero, then the Toggle bit is set to logic one. ...
Page 89
... ICS1893Y-10 - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893Y-10 provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Pins”). The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893Y-10 to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 7.11.5 ICS Reserved (bit 16.4) See Section 7.11.2, “ ...
Page 91
... ICS1893Y-10 - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893Y-10 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
Page 92
... Note: 1. For an explanation of acronyms used in 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893Y-10 to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 7.1.4.1, “ ...
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... ICS1893Y-10 - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893Y-10 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the value of this bit is determined by the Data Rate bit 0.13. ...
Page 94
... This bit has no definition in 10Base-T mode. 7.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893Y-10 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming 100Base data stream. If this bit is set to a logic: • ...
Page 95
... When the ICS1893Y-10 is receiving a packet, it examines each received Symbol to ensure the data is error free error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal. In addition, the ICS1893Y-10 sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic: • ...
Page 96
... Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control Register’s Auto-Negotiation Enable bit (bit 0.12) • One, it indicates that the ICS1893Y-10 has completed the auto-negotiation process and that the contents of Management Registers 4, 5, and 6 are valid. 7.12.11 100Base-TX Signal Detect (bit 17.3) The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode ...
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... Squelch inhibit 7.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893Y-10 port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
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... ICS1893Y-10 Data Sheet - Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893Y-10 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893Y-10 sets bit 18. logic zero. ...
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... ICS1893Y-10 - Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893Y-10 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • ...
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... ICS1893Y-10 Data Sheet - Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893Y-10 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
Page 101
... Zero, the NOD/REP input pin is pulled down, which instructs the operation code to operate in Node mode. • One, the NOD/REP input pin is pulled up, which instructs the ICS1893Y-10 to operate in Repeater mode. There are two primary differences between Node mode and Repeater mode. • ...
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... ICS1893Y-10 Data Sheet - Release 7.14.5 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893Y-10 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to logic: • Zero, the Twisted Pair Interface is operational. ...
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... TP_TXN 6 VDD 7 VDD 8 10TCSR 9 100TCSR 10 VSS 11 VSS 12 TP_RXP 13 TP_RXN 14 VDD 15 VDD 16 ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions ICS1893Y-10 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 103 48 TXD3 47 TXD2 46 TXD1 45 TXD0 44 TXEN 43 TXCLK 42 TXER 41 RXTRI 40 VSS ...
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... ICS1893Y-10 Data Sheet - Release 8.2 ICS1893Y-10 Pin Listings Table 8-1 lists the ICS1893Y-10 pins by pin number. Table 8-1. ICS1893Y-10 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 TP_CT 4 VSS 5 TP_TXP 6 TP_TXN 7 VDD 8 VDD 9 10TCSR 10 100TCSR 11 VSS 12 VSS 13 TP_RXP 14 TP_RXN 15 VDD ...
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... ICS1893Y-10 - Release 8.3 ICS1893Y-10 Pin Descriptions The tables in this section list the ICS1893Y-10 pins by their functional grouping. 8.3.1 Transformer Interface Pins Table 8-2 lists the pins for the transformer interface group of pins. Table 8-2. Transformer Interface Pins Pin Pin Pin Name ...
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... Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893Y-10 exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the address of the ICS1893Y-10 when either hardware mode or software mode. – An output pin following reset. In this case, this pin provides link status for the ICS1893Y-10 ...
Page 108
... These multi-function configuration pins are: – Input pins during either a power-on reset or a hardware reset. In this case, these pins configure the address of the ICS1893Y-10 when either hardware mode or software mode. – Output pins following reset. In this case, this pin provides link status for the ICS1893Y-10 ...
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... Input or Output DPXSEL 24 Input or Output ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Pin Description 10Base-T / 100Base-TX Select. The ‘Pin Type’ for this pin depends on the setting for the HW/SW pin (pin 23). When the HW/SW pin is set for: • ...
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... High, this pin selects Software mode operations. (Stream Cipher) Lock (Acquired). When the signal on this pin is logic: • Low, the ICS1893Y-10 does not have a lock on the data stream. • High, the ICS1893Y-10 has a lock on the data stream. Link Status. This pin is used to report the status of the link segment. When the signal on this pin is logic: • ...
Page 111
... Note: The signal on the CRS pin is not synchronous to the signal on either the RXCLK or TXCLK pin. Management Data Clock. The ICS1893Y-10 uses the signal on the MDC pin to synchronize the transfer of management information between the ICS1893Y-10 and the Station Management Entity (STA), using the serial MDIO data line. The MDC signal is sourced by the STA. Copyright © ...
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... The ICS1893Y-10, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893Y- used in an application that uses the mechanical MII specification, MDIO must have a 1.5 k Ω ±5% pull-up resistor at the ICS1893Y-10 end and Ω ±5% pull-down resistor at the station management end ...
Page 113
... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1893Y-10 acts to ensure that only one PHY is active at a time. Transmit Clock. The ICS1893Y-10 generates this clock signal to synchronize the transfer of data from the MAC/Repeater Interface to the ICS1893Y-10 ...
Page 114
... Transmit Enable. In MII mode: • The ICS1893Y-10 samples its TXEN signal to determine when data is available for transmission. When TXEN is asserted, the ICS1893Y-10 begins sampling the data nibbles on the transmit data lines TXD[3:0] synchronously with TXCLK. The ICS1893Y-10 then transmits this data over the media. • ...
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... COL – 49 CRS SCRS 50 MDC MDC 31 MDIO MDIO 30 ICS1893Y-10 Rev F 1/20/04 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Type No Collision (Detect). Connect For the 100M Symbol Interface, this pin connect. For more information, see Table Output Symbol Carrier Sense. This pin’s description is the same as that given in Input Management Data Clock ...
Page 116
... Pin Type Output (Symbol) Receive Clock. In Symbol Mode, the ICS1893Y-10 sources an SRCLK to a MAC/repeater. The SRCLK synchronizes the signals on the SRD[4:0] pins between the ICS1893Y-10 and the MAC/repeater. The following table contrasts the SRCLK behavior when the mode for the ICS1893Y-10 is either 10Base-T or 100Base-TX ...
Page 117
... Low, the MAC indicates it is not in a tri-state condition. • High, the MAC indicates tri-state condition. In this case, the ICS1893Y-10 acts to ensure that only one PHY is active at a time. (A PHY address of 00 also tri-states the MII interface.) Output Symbol Transmit Clock. ...
Page 118
... Management Data Input/Output. Output This pin’s description is the same as that given in Output 10M Receive Clock. In 10M Serial mode, the ICS1893Y-10 sources the 10RCLK to its MAC/repeater Interface. The 10RCLK synchronizes the data on the 10RD0 pin between the ICS1893Y-10 and the MAC/repeater. • ...
Page 119
... High, the MAC indicates that tri-state condition. In this case, the ICS1893Y-10 acts to ensure that only one PHY is active at a time. • If the PHY address is 00, the ICS1893Y-10 acts as if the RX-TRI pin is held high. Output 10M (Serial Interface) Transmit Clock. ...
Page 120
... ICS1893Y-10 Data Sheet - Release 8.3.5 Reserved Pins Table 8-8 lists the reserved pins. Table 8-8. Reserved Pins Pin Pin Pin Name Number Type REG 20 Input 8.3.6 Ground and Power Pins Table 8-9 lists the ground and power pins. Table 8-9. Ground and Power Pins ...
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... Stresses above these ratings can permanently damage the ICS1893Y-10. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1893Y-10 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... ICS1893Y-10 Data Sheet - Release 9.3 Recommended Component Values Table 9-3. Recommended Component Values for ICS1893Y-10 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std 802.3 requirements that drive the tolerance for the frequency of the oscillator. ...
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... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893Y-10. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 9-5 lists the 3 ...
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... Input High Voltage Input Low Voltage 9.4.4 DC Operating Characteristics for Media Independent Interface Table 9-7 lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1893Y-10. Table 9-7. DC Operating Characteristics for Media Independent Interface Parameter MII Input Pin Capacitance MII Output Pin Capacitance ...
Page 125
... Table 9-8. REF_IN Timing Time Parameter Period t1 REF_IN Duty Cycle t2 REF_IN Period Figure 9-2. REF_IN Timing Diagram REF_IN ICS1893Y-10 Rev F 1/20/04 Chapter 9 DC and AC Operating Conditions Conditions – – Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 125 Figure 9-2 Min ...
Page 126
... ICS1893Y-10 Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time periods. Table 9-9. Transmit Clock Timing ...
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... RXCLK Period t2c RXCLK Period t2d RXCLK Period Figure 9-4. Receive Clock Timing Diagram t1 RXCLK ICS1893Y-10 Rev F 1/20/04 Chapter 9 DC and AC Operating Conditions Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) 100M Symbol Interface (100Base-TX) 10M Serial Interface (10Base-T) t2 Copyright © 2004, Integrated Circuit Systems, Inc. ...
Page 128
... ICS1893Y-10 Data Sheet - Release 9.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • ...
Page 129
... TXD[3:0], TXEN, TXER Setup to TXCLK Rise t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise Figure 9-6. 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER ICS1893Y-10 Rev F 1/20/04 Parameter Conditions t1 t2 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 129 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893Y-10 Data Sheet - Release 9.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • RXD[3:0] • ...
Page 131
... MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893Y-10 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 9-8. MII Management Interface Timing Diagram MDC t1 ...
Page 132
... ICS1893Y-10 Data Sheet - Release 9.5.8 10M Serial Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI mapping of the 10M/100M MII TP_RXP and TP_RXN pins) • ...
Page 133
... Figure 9-10. 10M MII Receive Latency Timing Diagram † TP_RX RXCLK RXD 5 † Manchester encoding is not shown. ICS1893Y-10 Rev F 1/20/04 Parameter Conditions 10M MII 5 t1 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 133 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893Y-10 Data Sheet - Release 9.5.10 10M Serial Interface: Transmit Latency Table 9-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pins) • ...
Page 135
... Figure 9-12. 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD † TP_TX † Manchester encoding is not shown. ICS1893Y-10 Rev F 1/20/04 Parameter Conditions 10M MII Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 135 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893Y-10 Data Sheet - Release 9.5.12 MII / 100M Stream Interface: Transmit Latency Table 9-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... TXEN Sampled Asserted to CRS Assert t2 TXEN De-Asserted to CRS De-Asserted Figure 9-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 ICS1893Y-10 Rev F 1/20/04 Chapter 9 DC and AC Operating Conditions Parameter t2 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 137 Condi- Min. ...
Page 138
... ICS1893Y-10 Data Sheet - Release 9.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
Page 139
... Figure 9-16. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram † TP_RX RXCLK RXD † Shown unscrambled. ICS1893Y-10 Rev F 1/20/04 Chapter 9 DC and AC Operating Conditions Conditions t1 t2 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 139 Min. Typ. Max. ...
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... ICS1893Y-10 Data Sheet - Release 9.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • CRS • ...
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... Table 9-24. Power-On Reset Timing Time Period VDD ≥ 2 Reset Complete t1 Figure 9-18. Power-On Reset Timing Diagram 2.7 V VDD TXCLK Valid ICS1893Y-10 Rev F 1/20/04 Parameter Conditions t1 Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 141 Chapter 9 DC and AC Operating Conditions Min. Typ. ...
Page 142
... ICS1893Y-10 Data Sheet - Release 9.5.18 Reset: Hardware Reset and Power-Down Table 9-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 9-19 shows the timing diagram for the time periods ...
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... COL Heartbeat Assertion Delay from TXEN De-Assertion t2 COL Heartbeat Assertion Duration Figure 9-20. 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL ICS1893Y-10 Rev F 1/20/04 Chapter 9 DC and AC Operating Conditions Section 6.5.10, “10Base-T Operation: SQE Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 t2 Copyright © ...
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... ICS1893Y-10 Data Sheet - Release 9.5.20 10Base-T: Jabber Timing Table 9-27 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • COL Figure 9-21 shows the timing diagram for the time periods. ...
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... Table 9-28. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 9-22. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893Y-10 Rev F 1/20/04 Figure 9-22 shows the timing diagram for the time periods. Parameter Conditions 10Base-T 10Base Copyright © ...
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... ICS1893Y-10 - Release 9.5.22 Auto-Negotiation Fast Link Pulse Timing Table 9-29 lists the significant time periods for the ICS1893Y-10 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 9-23 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
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... ICS1893Y-10 - Release Chapter 10 Physical Dimensions of ICS1893Y-10 Package This section gives the physical dimensions for the ICS1893Y-10 package. • The lead count ( leads. • The nominal footprint (that is the body) is 10.0 mm. Table 10-1 lists the ICS1893Y-10 physical dimensions, which are shown in Table 10-1. ICS1893Y-10 Physical Dimensions ...
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... ICS1893Y-10 Data Sheet - Release Figure 10-1. ICS1893Y-10 Physical Dimensions ICS1893Y-10 Rev F 1/20/04 Chapter 10 Physical Dimensions of ICS1893Y- Standoff Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 148 Seating Plane January, 2004 ...
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... ICS1893Y-10 - Release Chapter 11 Ordering Information Figure 11-1. ICS1893Y-10 Ordering Information Part / Order Number ICS1893Y-10 ICS1893YI-10 1893YI-10 ICS1893Y-10LF 1893Y-10LF ICS1893YI-10LF 1893YI-10LF ICS1893Y-10 Rev F 1/20/04 Marking Package 1893Y-10 10x10 TQFP (Thin Quad Flat Pack) 10x10 TQFP (Thin Quad Flat Pack) 10x10 TQFP Lead Free 10x10 TQFP Lead Free Copyright © ...
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Integrated Circuit Systems, Inc. Corporate Headquarters: Silicon Valley: Web Site: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device ...