ICS1893BF IDT, Integrated Device Technology Inc, ICS1893BF Datasheet
ICS1893BF
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ICS1893BF Summary of contents
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... Sta Media-Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 Mb/s or 100Mb/s. The ICS1893BF is available in a 300-mil 48-lead SSOP pac performance circuitry with the ICS1893AF but is not a pin-for-pin replacement of the 1893AF. An application note for a dual footprint layout to accommodate ICS1893AF or ICS1893BF is available on the ICS website ...
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... ICS1893BF Data Sheet - Release Section Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Overview of the ICS1893BF............................................................................................. 14 3.1 100Base-TX Operation .......................................................................................... 15 3.2 10Base-T Operation ............................................................................................... 15 Chapter 4 Operating Modes Overview............................................................................................. 16 4.1 Reset Operations ................................................................................................... 17 4.1.1 General Reset Operations ..................................................................................... 17 4.1.2 Specific Reset Operations ..................................................................................... 18 4.2 Power-Down Operations ........................................................................................ 19 4 ...
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... ICS1893BF Data Sheet Rev Release Section 6.3 Functional Block: 100Base-X PCS and PMA Sublayers ........................................ 36 6.3.1 PCS Sublayer ........................................................................................................ 36 6.3.2 PMA Sublayer ........................................................................................................ 36 6.3.3 PCS/PMA Transmit Modules ................................................................................. 37 6.3.4 PCS/PMA Receive Modules .................................................................................. 37 6.3.5 PCS Control Signal Generation ............................................................................. 38 6.3.6 4B/5B Encoding/Decoding ..................................................................................... 39 6.4 Functional Block: 100Base-TX TP-PMD Operations ............................................. 39 6 ...
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... ICS1893BF Data Sheet - Release Section Chapter 7 Management Register Set ............................................................................................... 49 7.1 Introduction to Management Register Set ............................................................. 50 7.1.1 Management Register Set Outline ......................................................................... 50 7.1.2 Management Register Bit Access .......................................................................... 51 7.1.3 Management Register Bit Default Values .............................................................. 51 7.1.4 Management Register Bit Special Functions ......................................................... 52 7.2 Register 0: Control Register ................................................................................... 53 7.2.1 Reset (bit 0 ...
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... ICS1893BF Data Sheet Rev Release Section 7.5 Register 3: PHY Identifier Register ........................................................................ 63 7.5.1 OUI bits 19-24 (bits 3.15:10) .................................................................................. 63 7.5.2 Manufacturer's Model Number (bits 3.9:4) ............................................................. 63 7.5.3 Revision Number (bits 3.3:0) ................................................................................. 63 7.6 Register 4: Auto-Negotiation Register ................................................................... 65 7.6.1 Next Page (bit 4.15) ............................................................................................... 65 7.6.2 IEEE Reserved Bit (bit 4.14) .................................................................................. 66 7 ...
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... ICS1893BF Data Sheet - Release Section 7.11 Register 16: Extended Control Register ................................................................ 76 7.11.1 Command Override Write Enable (bit 16.15) ......................................................... 77 7.11.2 ICS Reserved (bits 16.14:11) ................................................................................. 77 7.11.3 PHY Address (bits 16.10:6) ................................................................................... 77 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) ..................................................... 77 7.11.5 ICS Reserved (bit 16.4) ......................................................................................... 77 7.11.6 NRZ/NRZI Encoding (bit 16 ...
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... ICS1893BF Data Sheet Rev Release Section 7.14 Register 19: Extended Control Register 2 ............................................................. 87 7.14.1 Node Configuration (bit 19.15) ............................................................................... 88 7.14.2 Hardware/Software Priority Status (bit 19.14) ........................................................ 88 7.14.3 Remote Fault (bit 19.13) ........................................................................................ 88 7.14.4 ICS Reserved (bits 19.12:10) ................................................................................. 88 7.14.5 Auto-MDI/MDIX (bits 19. 9:13)................................................................................ 88 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) ..................................................... 89 7 ...
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... Jabber Timing .....................................................................................127 9.5.19 10Base-T: Normal Link Pulse Timing ..................................................................128 9.5.20 Auto-Negotiation Fast Link Pulse Timing .............................................................129 Chapter 10 Physical Dimensions of ICS1893BF Package........................................................... 130 Chapter 11 Ordering Information.................................................................................................... 132 ICS1893BF, Rev. F, 5/13/10 Table of Contents Title Copyright © 2009, IDT, Inc. All rights reserved. ...
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... Page 28. Table 5-1 revised. – Page 83. Table 7-18. Correction made in Bit 17.3 row. – Page 92. Tables 8-1, -2, -3. ICS1893BF device number added to table titles, Table 8-2 deleted. Table numbering sequence changed to reflect the deletion. – Page 97. ICS1893BF device number added to [now] Table 8-3. New row added to table. Typo corrected in Signal Name column. In addition, ICS1893BF device number added to [now] Table 8-4. – ...
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... ICS1893BF Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor ...
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... Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893BF is a physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. (The ICS1890 is also a physical-layer device.) PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ...
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... All pin or signal names are provided in capital letters. • A pin name that includes a forward slash ‘/’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893BF functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... The terms ‘cleared’, ‘inactive’, and ‘de-asserted’ are synonymous. They do not necessarily infer logic zero. In reference to the ICS1893BF, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893BF, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © ...
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... Physical Medium Dependent sublayer (PMD) • Auto-Negotiation sublayer The ICS1893BF is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893BF can interface directly to the MAC. ...
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... Start-of-Frame delimiter (SFD not required that the ICS1893BF insert an SSD-like delimiter. When receiving data from the medium (such as a twisted-pair cable), the ICS1893BF uses the preamble to synchronize its receive clock. When the ICS1893BF receive clock establishes lock, it presents the preamble nibbles to its MAC Interface ...
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... The ICS1893BF register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893BF is configured to support the MAC Interface as a 10M MII or a 100M MII. The protocol on the Medium Dependent Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or full-duplex modes ...
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... Releases all MAC Interface pins, which takes a maximum of 640 ns after the reset condition is removed 4.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893BF reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893BF can connect its MAC Interface to a MAC while power is already applied to the MAC.) ICS1893BF, Rev ...
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... Section 4.1.1.1, “Entering Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893BF completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893BF sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... For example, if the ICS1893BF supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode ...
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... Operations The ICS1893BF 10Base-T mode provides 10Base-T physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 10Base-T mode, the ICS1893BF is a 10M translator between a MAC and the physical transmission medium. In 10Base-T mode, the ICS1893BF provides the following functions: • ...
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... ICS1893BF Data Sheet - Release 4.8 Auto-MDI/MDIX Crossover (New) The ICS1893BF includes the auto-MDI/MDIX crossover feature typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 wiring to the partners receive twisted pair signal pins and receive twisted pair to the partners transmit twisted pair. This is usually accomplished in the wiring plant ...
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... ICS1893BF Data Sheet Rev Release Chapter 5 Interface Overviews The ICS1893BF MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “Serial Management Interface” ...
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... ICS1893BF (that is, the ICS1893BF sources the TXCLK and RXCLK signals to the MAC). Clause 22 also defines as part of the MII a Carrier Sense signal (CRS) and a Collision Detect signal (COL). The ICS1893BF is fully compliant with these definitions and sources both of these signals to the MAC. When operating in: • ...
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... Status Register provides the ability to acquire the most-important status functions with a single MDIO read. Note: In the ICS1893BF, the MDIO and MDC pins remain active for all the MAC Interface modes (that is, 10M MII, 100M MII, 100M Symbol, and 10M Serial). 5.3 Twisted-Pair Interface For the twisted-pair interface, the ICS1893BF uses 1:1 ratio transformers for both transmit and receive ...
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... ICS1893BF Data Sheet - Release Figure 5-1. ICS1893BF Twisted Pair TP_AP 12 ICS1893BF TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z ICS1893BF, Rev. F, 5/13/10 System Ground Plane 1:1 61.9Ω 1% Center Tap 120 nH 3PF 61.9Ω 50Ω. 0.1 µF o 61.9Ω 1% ...
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... MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893BF supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 5 ...
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... If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893BF. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the bypass caps serve to adjust the final frequency of the crystal oscillation ...
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... A software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs. 3. Each multi-function configuration pin must be pulled either up or down with a resistor to establish the address of the ICS1893BF. LEDs may be placed in series with these resistors to provide a designated status indicator as described in Table 5-3. Caution: All pins listed in Table 5-3 must not float ...
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... ICS1893BF Data Sheet - Release Figure 5-3 shows typical biasing and LED connections for the ICS1893BF. Figure 5-3. ICS1893BF LED - PHY Interface P4RD P3TD 8 6 REC 10KΩ 10KΩ This circuit decodes to PHY address = 1. Notes: 1. All LED pins must be set during reset. ...
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... ICS1893BF Data Sheet Rev Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893BF functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” ...
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... The Media Independent Interface (MII) consists of two primary components interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893BF). This MAC-PHY part of the MII consists of three subcomponents synchronous Transmit interface that includes the following signals: ...
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... The ICS1893BF obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893BF and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893BF transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... ICS1893BF Data Sheet - Release 6. To indicate that the auto-negotiation process is complete, the ICS1893BF sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893BF Auto-Negotiation sublayer performs the following steps sets to logic one the Status Register’s Auto-Negotiation Complete bit (bit 1.5, which is also available in the QuickPoll register as bit 17 ...
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... ICS1893BF Data Sheet Rev Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893BF reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel ...
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... Physical Coding sublayer (PCS) and Physical Medium Attachment (PMA) sublayers. 6.3.1 PCS Sublayer The ICS1893BF 100Base-X PCS sublayer provides two interfaces: one to a MAC and the other to the ICS1893BF PMA sublayer. An ICS1893’s PCS sublayer performs the transmit, receive, and control functions and consists of the following: • ...
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... Both the PCS and PMA sublayers have Receive modules. 6.3.4.1 PCS Receive Module The ICS1893BF PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier ...
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... MAC Interface. Detection of an error forces the Receive state machine to assert the receive error signal (RX_ER) and wait for the next symbol. If the ICS1893BF Receive state machine detects a premature end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic one, and transitions to the IDLE State ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893BF to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see Error Code Test (bit 6 ...
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... The DSP-based adaptive equalizer uses a technique that compensates for a wide range of cable lengths. The optimizing parameter for the equalization process is the overall bit error rate of the ICS1893BF. This technique closes the loop on the entire data reception process and provides a very high overall reliability. ...
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... Section 4.6, “10Base-T 6.5.1 10Base-T Operation: Manchester Encoder/Decoder During data transmission the ICS1893BF acquires data from its MAC Interface in 4-bit nibbles. The ICS1893BF converts this data into a Manchester-encoded signal for presentation to its MDI, as required by the ISO/IEC specification Manchester-encoded signal, all logic: • ...
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... MAC Frame Preamble and continue as long as the ICS1893BF is receiving data. 6.5.4 10Base-T Operation: Idle An ICS1893BF transmits Normal Link Pulses on its MDI in the absence of data. During this time the link is Idle, and the ICS1893BF periodically transmits link pulses at a rate of one link pulse every compliance with the ISO/IEC 8802-3 standard ...
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... When a link is invalid and the Link Monitor Function detects the presence of data, the ICS1893BF does not transition the link to the valid state until after the reception of the present packet is complete. ...
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... The ICS1893BF has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state machines. These functions indicate whether the ICS1893BF is (1) transmitting data, (2) receiving data collision state (that is, the ICS1893BF is both transmitting and receiving data on its twisted-pair medium, as defined in the ISO/IEC 8802-3 standard). When the ICS1893BF is configured for: • ...
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... Normal Link Pulses (NLPs). In 10Base-T mode, an ICS1893BF transmits and receives NLPs when its link is in the Idle state. In 100Base-TX mode, an ICS1893BF transmits and receives NLPs during Auto-Negotiation. An STA can control this feature using the 10Base-T Operations Register bit 18.3, the Auto Polarity-Inhibit bit. When this bit is logic: • ...
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... In compliance with the ISO/IEC specification, the ICS1893BF implementation of the serial management interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the exchange of data. These pins remain active in all ICS1893BF MAC Interface modes (that is, the 10/100 MII, 100M Symbol, and 10M Serial interface modes). ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893BF does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... MDIO pin to logic zero for the second bit time. • Write, an ICS1893BF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 6.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893BF and the STA ...
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... ICS1893BF Data Sheet Rev Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table is a description of each bit. This chapter includes the following sections: • ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (IDT) Registers Table 7-2 lists the IDT-specific registers that the ICS1893BF implements. These registers enhance the performance of the ICS1893BF and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. IDT-Specific Registers Register Address 16 ...
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... Read/Write Read/Write Zero 7.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893BF sets all Management Register bits to their default values after a reset. ICS1893BF Management Register bits. Table 7-4. Range of Possible Valid Default Values for ICS1893BF Register Bits Default Condition – ...
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... STA access. The SC bits have a default value of logic zero and are triggers to begin execution of a function. When the STA writes a logic one bit, the ICS1893BF begins executing the function assigned to that bit. After the ICS1893BF completes executing the function, it clears the bit to indicate that the action is complete ...
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... Reserved bits. 7.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893BF software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893BF is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893BF isolates this bit 0.13 and uses the 10/100SEL input pin to establish the data rate for the ICS1893BF. In this Hardware mode: – Bit 0.13 is undefined. ...
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... Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893BF isolates itself from the MAC Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893BF does not isolate its MAC Interface. 7.2.7 Restart Auto-Negotiation (bit 0.9) This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is logic one) ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893BF is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893BF isolates bit 0.8 and uses the DPXSEL input pin to establish the Duplex mode for the ICS1893BF. In this Hardware mode: – Bit 0.8 is undefined. ...
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... As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value to all Reserved bits. 7.3.1 100Base-T4 (bit 1.15) The STA reads this bit to learn if the ICS1893BF can support 100Base-T4 operations. Bit 1.15 of the ICS1893BF is permanently set to logic zero, which informs an STA that the ICS1893BF cannot support 100Base-T4 operations. ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893BF supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893BF Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893BF implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893BF ...
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... Zero, then the ICS1893BF sets bit 1.4 to logic zero. • One, then the ICS1893BF sets bit 1.4 to logic one. In this case, the remote link partner is reporting the detection of a fault, which typically occurs when the remote link partner is having a problem with its receive channel ...
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... ICS1893BF Data Sheet Rev Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893BF detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893BF Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893BF Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... ICS1893BF Data Sheet - Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by the ISO/IEC specification set, the PHY Identifier Registers (Registers 2 and 3) include a unique, 32-bit PHY Identifier composed from the following: • ...
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... ICS1893BF Data Sheet Rev Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from least significant to most significant, and from left to right ...
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... The most-significant 6 bits of register 3 (that is, bits 3.15:10) include OUI bits 19 through 24. OUI bit 19 is stored in bit 3.15, while OUI bit 24 is stored in bit 3.10. 7.5.2 Manufacturer's Model Number (bits 3.9:4) The model number for the ICS1893BF is 4 (decimal stored in bit 3.9:4 as 00100b. 7.5.3 Revision Number (bits 3.3:0) Table 7-10 lists the valid ICS1893BF revision numbers, which are 4-bit binary numbers stored in bits 3 ...
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... Zero, then the ICS1893BF indicates to its remote link partner that these features are disabled. (Although the default value of this bit is logic zero, the ICS1893BF does support the Next Page function.) • One, then the ICS1893BF advertises to its remote link partner that this feature is enabled. ...
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... Code Word that the ICS1893BF exchanges with its remote link partner. The ICS1893BF sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893BF does not detect a link fault, it clears bit 4.13 to logic zero. ...
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... One (that is, enabled), the ICS1893BF executes the auto-negotiation process and advertises its capabilities to the remote link partner. The TAF bits (bits 4.8:5) determine the capabilities that the ICS1893BF advertises to its remote link partner. For the ICS1893BF, all of these bits 4.8:5 are set to logic one, indicating the ability of the ICS1893BF to provide these technologies. ...
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... During the auto-negotiation process, the ICS1893BF advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
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... Zero, it indicates that the remote link partner has not received the ICS1893BF Link Control Word. • One, it indicates to the ICS1893BF / STA that the remote link partner has acknowledged reception of the ICS1893BF Link Control Word. 7.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations ...
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... Next Page bit in its Link Control Word. 7.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893BF to support the Next Page features of the auto-negotiation process. The ICS1893BF sets this bit to a logic one to indicate that it can support these features ...
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... ICS1893BF Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893BF cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893BF can comply with the message. 7.9.5 Toggle (bit 7.11) The Toggle (T) bit (bit 7.11) is used to synchronize the transmission of Next Page messages with the remote link partner ...
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... ICS1893BF Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893BF cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893BF can comply with the message. If the previous Next Page Link Control Word Toggle bit has a value of logic: • Zero, then the Toggle bit is set to logic one. ...
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... ICS1893BF Data Sheet - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893BF provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Pins”). The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893BF to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 7.11.5 ICS Reserved (bit 16.4) See Section 7.11.2, “ ...
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... ICS1893BF Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893BF to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
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... Note: 1. For an explanation of acronyms used in 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893BF to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 7.1.4.1, “ ...
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... ICS1893BF Data Sheet - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893BF is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the value of this bit is determined by the Data Rate bit 0.13. ...
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... This bit has no definition in 10Base-T mode. 7.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893BF has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming 100Base data stream. If this bit is set to a logic: • ...
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... When the ICS1893BF is receiving a packet, it examines each received Symbol to ensure the data is error free error occurs, the port indicates this condition to the MAC by asserting the RXER signal. In addition, the ICS1893BF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic: • ...
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... The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893BF. During reception of a valid packet, the ICS1893BF examines each symbol to ensure that the data being passed to the MAC Interface is error free. If two consecutive Idles are encountered, it indicates this condition to the MAC by setting this bit ...
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... Squelch inhibit 7.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893BF port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
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... ICS1893BF Data Sheet Rev Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893BF has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893BF sets bit 18. logic zero. ...
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... ICS1893BF Data Sheet - Release 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893BF from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • ...
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... ICS1893BF Data Sheet Rev Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893BF operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Section 7.11.2, “ICS Reserved (bits 7.14.5 Auto-MDI/MDIX (bits 19. 9:8) (New) The ICS1893BF includes the Auto-MDI/MDIX crossover feature. The Auto-MDI/MDIX feature automatically selects the correct MDI or MDIX configuration to match the cable plant by automatically swapping transmit and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes using either the AMDIX_EN (pin 10 writing (bits 19 ...
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... AMDIX_EN [19:9] MDI_MODE [19:8] MDIO register 13h bit 8 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893BF provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to logic: • ...
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... ICS1893BF Data Sheet - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893BF Pin Diagram POAC 1 VSS 2 P1CL 3 P2LI 4 VSS 5 P3TD 6 VDD 7 P4RD 8 10/100 9 AMDIX_EN 10 VSS 11 TP_AP 12 TP_AN 13 VDD 14 TP_BN 15 TP_BP 16 VSS 17 VDD 18 10TCSR 19 100TCSR 20 VSS 21 VDD 22 RESET_N 23 VDD 24 ICS1893BF, Rev. F, 5/13/10 ...
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... ICS1893BF Data Sheet Rev Release 8.2 ICS1893BF Pin Descriptions Table 8-1. ICS1893BF MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 COL CRS Table 8-2. ICS 1893BF Multifunction Pins: PHY Address and LED Pins ...
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... Transformer connections on the ICS1893BF signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8.4. The previous TP_CT pin on the ICS1893AF is not used with the ICS1893BF. The typical Twisted Pair Transformers connections are shown in Chapter 5. The transformer must be 1:1 ratio and symetrical for 10/100 MDI/MDIX applications since the transmit twisted pair and receive twisted pair are interchangeable ...
Page 93
... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893BF PHY Address Bit 1. – An output pin following reset. In this case, this pin provides collision status for the ICS1893BF input pin: • ...
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... When the signal on this pin is: – De-asserted, this state indicates the ICS1893BF does not have a link. – Asserted, this state indicates the ICS1893BF has a valid link. Caution: This pin must not float. (See the notes at “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins” ...
Page 95
... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893BF when either hardware mode or software mode. – An output pin following reset. In this case, this pin provides activity status of the ICS1893. ...
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... This pin is used with a crystal. Input (System) Reset (Active Low). • When the signal on this active-low pin is logic: – Low, the ICS1893BF is in hardware reset. – High, the ICS1893BF is operational. • For more information on hardware resets, see the following: – Section 4.1.2.1, “Hardware Reset” ...
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... Note: The signal on the CRS pin is not synchronous to the signal on either the RXCLK or TXCLK pin. Management Data Clock. The ICS1893BF uses the signal on the MDC pin to synchronize the transfer of management information between the ICS1893BF and the Station Management Entity (STA), using the serial MDIO data line. The MDC signal is sourced by the STA. Copyright © ...
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... The ICS1893BF, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893BF used in an application that uses the mechanical MII specification, MDIO must have a 1.5 kΩ ±5% pull-up resistor at the ICS1893BF end and a 2 kΩ ±5% pull-down resistor at the station management end ...
Page 99
... Errors are detected during the reception of valid frames – A False Carrier is detected Note ICS1893BF asserts a signal on the RXER pin upon detection of a False Carrier so that repeater applications can prevent the propagation of a False Carrier. 2. The RXER signal always transitions synchronously with RXCLK. ...
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... TXD0 is the least-significant bit and TXD3 is the most-significant bit of the MII transmit data nibble received from the MAC. • The ICS1893BF samples its TXEN signal to determine when data is available for transmission. When TXEN is asserted, the signals on a the TXD[3:0] pins are sampled synchronously on the rising edges of the TXCLK signal ...
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... ICS1893BF Data Sheet Rev Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions Pin No ...
Page 102
... ICS1893BF Data Sheet - Release 8.3 ICS1893BK Pin Diagram with MDIX Pinout (56L, 8x8 MLF2) 10/100 1 AMDIX_EN 2 VSS 3 TP_AP 4 TP_AN 5 VDD 6 VDD 7 TP_BN 8 TP_BP 9 VSS 10 VDD_A 11 10TCSR 12 100TCSR 13 VSS 14 ICS1893BF, Rev. F, 5/13/10 Chapter 8 Pin Diagram, Listings, and Descriptions ICS1893BK 8x8 56L MLF2 Copyright © ...
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... ICS1893BF Data Sheet Rev Release 8.3.1 ICS1893BK Pin Descriptions The ICS1893BK Pin Signal Descriptions are identical in function to the ICS1893BF except for the Pin Numbers. See section 8.1 for descriptions. Table 8-9. ICS1893BK MAC Interface Pins Signal Name MDIO MDC RXD3 RXD2 ...
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... ICS1893BF Data Sheet - Release Table 8-11. ICS1893BK Configuration Pins Signal Name REF_IN REF_OUT RESETn 8.3.2 Transformer Interface Pins Transformer connections on the ICS1893BK signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8-12. The previous TP_CT pin used on the ICS1893AF is not used with the ICS1893BK. The typical Twisted Pair Transformers connections are shown in Chapter 5 ...
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... ICS1893BF Data Sheet Rev Release 8.3.3 Ground and Power Pins Table 8-13. ICS1893BK Ground and Power Pins Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ICS1893BF, Rev ...
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... Stresses above these ratings can permanently damage the ICS1893BF. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the ICS1893BF at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
Page 107
... VDD changes. Lowering the 12.1K value will lower the 100baseT amplitude. 5. The ICS1893BF 10baseT amplitude is below the IEEE spec but is adequate for 200m operation. This is the effect of additional MUXes added for the Auto-MDIX function. ICS1893BF, Rev. F, 5/13/10 ...
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... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893BF. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 9-5 lists the 3 ...
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... Input High Voltage Input Low Voltage 9.4.4 DC Operating Characteristics for Media Independent Interface Table 9-7 lists DC operating characteristics for the Media Independent Interface (MII) for the ICS1893BF. Table 9-7. DC Operating Characteristics for Media Independent Interface Parameter MII Input Pin Capacitance MII Output Pin Capacitance MII Output Drive Impedance ICS1893BF, Rev ...
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... ICS1893BF Data Sheet - Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the time periods. Note: The REF_IN switching point is 50% of VDD. ...
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... ICS1893BF Data Sheet Rev Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time periods. Table 9-9. Transmit Clock Timing ...
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... ICS1893BF Data Sheet - Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for the time periods. Table 9-10. MII Receive Clock Timing ...
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... ICS1893BF Data Sheet Rev Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • ...
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... ICS1893BF Data Sheet - Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • TXD[3:0] • TXEN • TXER Figure 9-6 shows the timing diagram for the time periods ...
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... ICS1893BF Data Sheet Rev Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • ...
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... MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893BF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 9-8. MII Management Interface Timing Diagram MDC MDIO ...
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... ICS1893BF Data Sheet Rev Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, the MII TP_RXP and TP_RXN pins) • ...
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... ICS1893BF Data Sheet - Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... ICS1893BF Data Sheet Rev Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893BF Data Sheet - Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893BF Data Sheet Rev Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... ICS1893BF Data Sheet - Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
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... ICS1893BF Data Sheet Rev Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • ...
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... ICS1893BF Data Sheet - Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 shows the timing diagram for the time periods. ...
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... ICS1893BF Data Sheet Rev Release 9.5.16 Reset: Hardware Reset and Power-Down Table 9-23 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 9-17 shows the timing diagram for the time periods ...
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... ICS1893BF Data Sheet - Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • COL Figure 9-18 shows the timing diagram for the time periods ...
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... ICS1893BF Data Sheet Rev Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • COL Figure 9-19 shows the timing diagram for the time periods ...
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... ICS1893BF Data Sheet - Release 9.5.19 10Base-T: Normal Link Pulse Timing Table 9-26 lists the significant time periods for the 10Base-T Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width ...
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... ICS1893BF Data Sheet Rev Release 9.5.20 Auto-Negotiation Fast Link Pulse Timing Table 9-27 lists the significant time periods for the ICS1893BF Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 9-21 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
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... ICS1893BF Data Sheet - Release Chapter 10 Physical Dimensions of ICS1893BF Package Figure 10-1. ICS1893BF 300 mil SSOP Physical Dimensions ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 130 May, 2010 ...
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... ICS1893BF Data Sheet Rev Release Figure 10-2. ICS1893BK Thermally Enhanced, Very Thin, Fine Pitch, Quad Flat / No Lead Plastic Package ICS1893BF, Rev. F, 5/13/10 Chapter 10 Physical Dimensions of ICS1893BF Copyright © 2009, IDT, Inc. All rights reserved. 131 May, 2010 ...
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... ICS1893BF Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893BF. Part / Order Number ICS1893BFLF 1893BFLF ICS1893BFLFT 1893BFLF ICS1893BFILF 1893BFILF ICS1893BFILFT 1893BFILF ICS1893BKLF 1893BKLF ICS1893BKLFT 1893BKLF ICS1893BKILF 1893BKILF ICS1893BKILFT 1893BKILF 11.1 Marking Diagram Notes: 1. Line 3: ###### = Lot number. ...
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... ICS1893BF Data Sheet Rev Release Integrated Device Technology, Inc. Web Site: ICS1893BF, Rev. F, 5/13/10 http://www.idt.com Copyright © 2009, IDT, Inc. All rights reserved. 133 Chapter 11 Ordering Information May, 2010 ...