ICS1893BF IDT, Integrated Device Technology Inc, ICS1893BF Datasheet - Page 81

• Manufacturer Part Number: ICS1893BF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893BF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893BF

7.12.4 100Base-TX Receive Signal Lost (bit 17.10)
7.12.5 100Base PLL Lock Error (bit 17.9)
ICS1893BF, Rev. F, 5/13/10
Note:
Table 7-19. Auto-Negotiation State Machine (Progress Monitor)
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893BF has lost its
100Base-TX Receive Signal. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893BF has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
Auto-Negotiation State Machine
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed
Successfully
Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
One, it indicates the Receive Signal was lost since either the last read or reset of this register.
Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
ICS1893BF Data Sheet Rev. F - Release
An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
and
and
Section 7.1.4.2, “Latching Low
Section 7.1.4.2, “Latching Low
Complete Bit
Negotiation
(Bit 17.4)
Copyright © 2009, IDT, Inc.
Auto-
All rights reserved.
0
0
0
0
0
0
0
0
1
81
Auto-Negotiation Progress Monitor
Monitor Bit 2
Negotiation
(Bit 17.13)
Auto-
0
0
0
0
1
1
1
1
0
Bits”.)
Bits”.)
Monitor Bit 1
Chapter 7 Management Register Set
Negotiation
(Bit 17.12)
Auto-
0
0
1
1
0
0
1
1
0
Monitor Bit 0
Negotiation
(Bit 17.11)
Auto-
0
1
0
1
0
1
0
1
0
Section
Section
May, 2010