ICS1893BF IDT, Integrated Device Technology Inc, ICS1893BF Datasheet - Page 46

• Manufacturer Part Number: ICS1893BF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893BF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893BF

6.5.14 10Base-T Operation: Isolation Transformer
6.6 Functional Block: Management Interface
6.6.1 Management Register Set Summary
6.6.2 Management Frame Structure
ICS1893BF, Rev. F, 5/13/10
When an ICS1893BF detects a reversed signal polarity on its Twisted-Pair Receiver pins and the Auto
Polarity-Inhibit bit is also logic zero (enabled), the ICS1893BF (1) automatically corrects the data stream
and (2) sets its Polarity Reversed bit (bit 18.14) to logic one, to indicate to the STA that this situation exists.
Bit 18.14 is a latching high (LH) bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits”
Note:
The 10Base-T Isolation Transformer operates the same as the 100Base-TX Isolation Transformer. In fact,
in a typical ICS1893BF application they are the same unit. For more information, see
“100Base-TX Operation: Isolation
As part of the MAC Interface, the ICS1893BF provides a two-wire serial management interface which
complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to
exchange control, status, and configuration information between a Station Management entity (STA) and
the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of
management registers. The ISO/IEC standard specifies the following components of this serial
management interface:
•
•
•
In compliance with the ISO/IEC specification, the ICS1893BF implementation of the serial management
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the
exchange of data. These pins remain active in all ICS1893BF MAC Interface modes (that is, the 10/100
MII, 100M Symbol, and 10M Serial interface modes).
The ICS1893BF implements a Management Register set that adheres to the ISO/IEC standard. This
register set (discussed in detail in
Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the
exchange of configuration, control, and status data between a PHY, such as an ICS1893BF, and an STA.
All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange
data through a pre-defined register set.
The ICS1893BF complies with the ISO/IEC defined Management Frame Structure and protocol. This
structure supports both read and write operations.
Structure.
A set of registers
The frame structure
The protocol
ICS1893BF Data Sheet - Release
The ICS1893BF will not complete the Auto-MDIX function for an inverted polarity cable. This
is a rare event with modern manufactured cables. Full Auto-Negotiation and Auto Polarity
Correction will complete when the Auto-MDIX function is disabled. Software control for the
Auto-MDIX function is available in MDIO Register 19 Bits 9:8.
(Section 6.6.1, “Management Register Set
(Section 6.6.2, “Management Frame
Chapter 7, “Management Register
Transformer”.
and
Copyright © 2009, IDT, Inc.
Section 7.1.4.2, “Latching Low
All rights reserved.
46
Table 6-1
Structure”)
summarizes the Management Frame
Summary”)
Set”) includes the mandatory ‘Basic’
Bits”.)
Chapter 6 Functional Blocks
Section 6.4.7,
May, 2010