ICS1893BF IDT, Integrated Device Technology Inc, ICS1893BF Datasheet - Page 78

• Manufacturer Part Number: ICS1893BF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893BF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893BF

7.11.7 Invalid Error Code Test (bit 16.2)
7.11.8 ICS Reserved (bit 16.1)
7.11.9 Stream Cipher Disable (bit 16.0)
ICS1893BF, Rev. F, 5/13/10
The Invalid Error Code Test bit allows an STA to force the ICS1893BF to transmit symbols that are typically
classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the
serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC
4B/5B definition.
When this bit is logic:
•
•
Table 7-17. Invalid Error Code Translation Table
See
The Stream Cipher Disable bit allows an STA to control whether the ICS1893BF employs the Stream
Cipher Scrambler in the transmit and receive data paths. When this bit is set to logic:
•
•
Note:
Symbol
Zero, the ISO/IEC defined 4B/5B translation takes place.
One – and the TXER signal is asserted by the MAC – the MII input nibbles are translated according to
Table
Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1893BF transmits unscrambled IDLES, and so forth.
V (S)
Section 7.11.2, “ICS Reserved (bits
V
V
V
V
H
V
V
R
V
V
K
V
ICS1893BF Data Sheet - Release
T
J
I
The Stream Cipher Scrambler can be used only for 100-MHz operations.
7-17.
Invalid Code
Invalid Code
Invalid Code
Invalid Code
Error
Invalid Code
Invalid Code
ESD
Invalid Code
ESD
Invalid Code
SSD
Invalid Code
Invalid Code
SSD
Idle
Meaning
MII Input
Nibble
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
Copyright © 2009, IDT, Inc.
16.14:11)”, the text for which also applies here.
Translation
All rights reserved.
00000
00001
00010
00100
00101
00000
10001
10000
00011
00110
01101
01100
11001
11000
00111
11111
78
Chapter 7 Management Register Set
May, 2010