ICS1893BF IDT, Integrated Device Technology Inc, ICS1893BF Datasheet - Page 98

• Manufacturer Part Number: ICS1893BF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893BF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 1893BF

ICS1893BF, Rev. F, 5/13/10
Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued)
MDIO
RXCLK
Name
Pin
ICS1893BF Data Sheet - Release
Number
Pin
26
34
Output
Output
Input/
Type
Pin
Management Data Input/Output.
The signal on this pin can be tri-stated and can be driven by one of the
following:
All transfers and sampling are synchronous with the signal on the MDC
pin.
Receive Clock.
The ICS1893BF sources the RXCLK to the MAC interface. The
ICS1893BF uses RXCLK to synchronize the signals on the following pins:
RXD[3:0], RXDV, and RXER. The following table contrasts the behavior
on the RXCLK pin when the mode for the ICS1893BF is either 10Base-T
or 100Base-TX.
Note: If the ICS1893BF is to be used in an application that uses the
•
•
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893BF.
The ICS1893BF, to transfer status information.
The RXCLK frequency is 2.5
MHz.
The ICS1893BF generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893BF switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893BF is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once per
packet.
Copyright © 2009, IDT, Inc.
mechanical MII specification, MDIO must have a 1.5 kΩ ±5%
pull-up resistor at the ICS1893BF end and a 2 kΩ ±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
All rights reserved.
10Base-T
98
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
The RXCLK frequency is 25 MHz.
The ICS1893BF generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the ICS1893BF
uses the REF_IN clock to
generate the RXCLK.
While the ICS1893BF is bringing
up a link, a clock phase change of
up to 360 degrees can occur.
The RXCLK aligns once, when
the link is being established.
100Base-TX
May, 2010