DP83848CVVX/NOPB National Semiconductor, DP83848CVVX/NOPB Datasheet - Page 23

• Manufacturer Part Number: DP83848CVVX/NOPB
• Description: TXRX ETHERNET PHYTER 48-LQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of DP83848CVVX/NOPB

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: DP83848C-POE-EK - BOARD EVALUATION DP83848CDP83848C-MAU-EK - BOARD EVALUATION DP83848C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DP83848CVVX

3.4.3 Serial Management Preamble Suppression
The DP83848C supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) deter-
mines that all PHYs in the system support Preamble Sup-
pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.
The DP83848C requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
Read Operation
Write Operation
MII Management
MDIO
MDIO
MDC
MDC
MDIO
Serial Protocol
(STA)
(PHY)
(STA)
Z
Idle
Z
Idle
Z
Z
0
0
Start
Start
1 1
1
Opcode
(Read)
Opcode
(Write)
0
0 0
1
0
(PHYAD = 0Ch)
(PHYAD = 0Ch)
PHY Address
PHY Address
1 1 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Figure 5. Typical MDC/MDIO Write Operation
Figure 4. Typical MDC/MDIO Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Table 5. Typical MDIO Frame Format
Register Address
Register Address
(00h = BMCR)
(00h = BMCR)
Z
Z
Z
23
1
TA
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
TA
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre-
amble Suppression is supported.
While the DP83848C requires an initial preamble
sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subse-
quent transaction. A minimum of one idle bit between man-
agement transactions is required as specified in the IEEE
802.3u specification.
0 0 0
0 0
0 0 0
Register Data
Register Data
0
0 0 0 0 0 0 0 0
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Z
Idle
Z
Z
Idle
Z