CorePCI Eval Board MICROSEMI, CorePCI Eval Board Datasheet - Page 12

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: MICROSEMI

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

CorePCI Target Function
CorePCI Target function acts like a slave on the PCI bus.
The Target controller monitors the bus and checks for
hits to either configuration space or to the address space
defined in its base address registers (BARs). When a hit is
detected, the Target controller notifies the backend and
then acts to control the flow of data between the PCI bus
and the backend.
Supported Target Commands
Table 7 on page 12
the current CorePCI Target implementation. If required,
I/O support, and thus I/O commands, can be eliminated
from
customization options.
I/O Read (0010) and Write (0011)
The I/O read command is used to read data mapped into
I/O address space. CorePCI will not check to verify the
consistency of the address and byte enables. This and any
additional error checking is left for implementation by
the user. The I/O write command is used to write data
mapped into I/O address space. In this case, the write is
qualified by the byte enables. The default I/O space size
is 256 bytes.
Memory Read (0110) and Write (0111)
The memory read and write commands are used to read
data in memory-mapped address space. The baseline
memory core supports 4 megabytes for the 32-bit core
and 8 megabytes for the 64-bit core, which can be
located anywhere in 32-bit address space. The memory
size may be set to any value using the MADDR_WIDTH
customization constant.
Configuration Read (1010) and Write (1011)
The configuration read command is used to read the
configuration space of each device. The configuration
write command is employed to write information into
the configuration space. The device is selected if its IDSEL
signal is asserted and AD[1:0] are '00'b. Additional
address bits are defined as follows:
1 2
CorePCI v5.41
• AD[7:2] contain one of 64 DWORD addresses for
• AD[10:8] indicate which device of a multi-function
• AD[31:11] are "don’t cares."
the configuration registers.
agent is addressed. The core does not support
multi-function devices and these bits should be
'000'b.
the
design
lists the PCI commands supported in
by
setting
the
appropriate
v4.0
Table 7 • Supported PCI Target Commands
Supported Cycle Types
CorePCI Target will perform either single DWORD or
burst transactions depending on the request from the
system Master. If the backend is unable to deliver data,
the Target will respond with either a PCI Retry or
Disconnect, either with or without data. If the system
Master requests a transfer that the backend is not able
to perform, a Target abort can be initiated by the
backend.
Target Configuration Space
The PCI specification requires a 64-byte configuration
space (header) to define various attributes of the PCI
Target, as shown in
shown in bold are implemented, including the two base
address registers. None of the remaining registers are
included in the baseline implementation and will return
zeroes when read.
In the Target-only function, one additional configuration
register, 48h, is used to define backend interrupt control
and status. For other functions, this information is
contained in the DMA control register.
C/BE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Table 8 on page
13. All registers
No
Yes
Yes
Yes
Yes
No
Yes
No
Supported
No
Yes
–
–
–
–
Yes
Yes